基于FPGA便携式BPC定时接收机设计.pdf

时间频率学报 1 基于FPGA的便携式 BPC 定时接收机设计 1,2,3 1,3 1,3 刘小花 ，许林生 ，华宇 摘要：介绍了一种基于 FPGA 的便携式低频时码接收机系统的设计方案。该接收机的特点是体 积小，功耗低，方便户外工作人员携带。描述了该接收机的硬件系统结构,给出了软件算法。 硬件结构中，使用了 ALTERA 公司的 EP2C70F672C8 芯片，软件部分在 QuartusⅡ开发环境下完 成。系统测试结果表明，按本方案设计的接收机集成度高，可靠性好，易扩展，易升级，具有 一定的实用价值。 关 键 词：低频时码；数字接收机；数字滤波；现场可编程门阵列（FPGA） 中图分类号：TN965.5 文献标志码：A 文章编号：1674-0637(2012)02-0088-08 A design of portable low frequency time-code receiver based on FPGA LIU Xiao-hua1,2,3, XU Lin-sheng1,3, HUA Yu1,3 (1. National Time Service Center, Chinese Academy of Sciences, Xi′an 710600, China; 2. Graduate University of Chinese Academy of Science, Beijing 100039, China; 3. Key Laboratory of Precision Navigation and Timing Technology, National Time Service Center, Chinese Academy of Sciences, Xi′an 710600, China) Abstract: A design of portable low frequency time-code receiver based on FPGA(field programmable gate array) is introduced. The receiver is characterized by small volume and low power consumption, and it is very convenient to carry it outdoors. The design of hardware structure and software algorithm is described in this paper. The chip of EP2C70F672C8 produced by the ALTERA company is adopted in the hardware structure, and the software design is completed in Quartus Ⅱ environment. The experimental r