2低噪放芯片电路设计.DOCVIP

Ka频段自给偏置低噪声放大器MMIC设计 杨自强 杨涛 刘宇 电子科技大学 电子工程学院, 四川 成都 610054 摘要：设计了一个Ka频段低噪声放大器MMIC，该芯片采用四级放大的结构，通过调节有源器件的几何尺寸(栅宽和叉指数)和源极串联负反馈，减小最佳噪声匹配点（）和共轭匹配点（）之间的距离，使低噪声放大器同时获得最佳噪声匹配和共轭匹配。另一方面，该放大器芯片采用了自给偏置设计，实现单电源供电。该放大器芯片采用商用的0.18-μm pHEMT工艺制造，芯片面积为3×1mm2。经测试，该芯片在26-40GHz频率范围内，实现增益大于18dB，35GHZ处噪声系数约为2.7dB。 关键字：低噪声放大器；Ka频段；微波单片集成电路 The design of a Ka-band self-biasedlow noise amplifier MMIC Yang Zi-qiang, Yang Tao, Liu Yu School of Electronics Engineering, University of Electronic Science and Technology of China, Chengdu 610054, China Abstract: A Ka-band four-stage low noise amplifier (LNA) monolithic microwave integrated circuit (MMIC) has been developed. The gate width of the active device and the source series feedback are chosen carefully to minimize the distance between and , where is the load impedance providing the minimum noise figure and is a conjugate reflection coefficient of , and then the LNA can achieve optimal noise match and conjugate match simultaneously. For the application of self-bias technique, the LNA is biased from a single power supply. The LNA has achieved a broadband performance with a gain of more than 18 dB, a noise figure of less than 2.3 dB in the RF frequency of 26.5 to 40 GHz. The chip size is 3? mm2. The amplifier， which is fabricated by a commercial 0.18-μm pseudomorphic high electron-mobility transistor (pHEMT) process, has achieved a gain of more than 18 dB in the frequency range of 26 to 40 GHz and a noise figure of 2.7 dB at 35 GHz. The chip size is 3×1 mm2. Key Words: low noise amplifier；Ka-band；monolithic microwave integrated circuit  1 引言( 随着毫米波技术的讯速发展，越来越多的通信和雷达系统被设计工作在毫米波频段，这就对毫米波集成接收前端以及毫米波单片集成电路（MMIC）有大量的需求[1]。单片电路具有高可靠性、低成本、宽频带以及小、轻等优点，是毫米波电路的发展方向。低噪声放大器是射频前端系统的关键单元之一，它位于接收芯片的第一级，直接与天线相连。由于其位于接收芯片的第一级，所以它的噪声特性将大大影响整个系统的噪声特性。国外关于Ka频段LNA芯片的报道非常多[2,3]，很多公司都有成熟的产品推出，国内也有研究所开展LNA芯片的研究[4,5]，开发具有自主知识产权的LNA芯片产品，实现芯片的国产化具有重要意义。 2 低噪放芯片电路设计 低噪声放大器的设计要综合考虑很多指标，如：增益、噪声、功耗、阻抗匹配、稳定性和线性度等。它必须在一定的功耗条件下，提供足够的增益、优异的噪声性能、良好的线性度和输入输出匹配。足够的增