基于无关配置位分布的FPGA 选择性三模冗余方法.PDF

计 算 机 研 究 与 发 展 DOI:10.7544/issn1000-1239.2015.******** Journal of Computer Research and Development 卷(期):起止页,年 基于无关配置位分布的FPGA 选择性三模冗余方法 郑美松1 ，2 王子龙1 ，2 涂吉1 ，2 王骏也1 ，2 李立健1 1 中科院自动化所，北京 100190 2 中科院研究生院，北京 100039 (meisong.zheng@ia.ac.cn) Selective Triple Modular Redundancy for FPGAs Based on Don’t Care Configuration Bits Distribution Zheng Meisong1,2 , Wang Zilong1,2, Tu Ji1,2, Wang Junye1,2, and Li Lijian1 1 (Institute of Automation, Chinese Academy of Science, Beijing 100 190) 1 (Graduate University, Chinese Academy of Science, Beijing 100039) Abstract As device size shrinks, SRAM-based FPGAs are increasingly prone to be affected by single-event upsets (SEUs). Triple module redundancy (TMR) hardening technique is the most effective and applicable method nowadays, but it is really expensive in terms of area and power costs. Selective TMR can greatly reduce the area overhead with a small loss of SEU immunity, hence in this work, we propose a new strategy for selective TMR based on don ’t care configuration bits distribution. Don’t care configuration bits are calculated by means of windowing for each LUTs in the circuit, with the statistics of don’t care configuration bits, LUTs are classified into two sets: SEU-sensitive or SEU-insensitive. SEU-insensitive LUTs remain unchanged whereas SEU-sensitive LUTs have to be tripled and voted. The triplication operates on Look-up table (LUT) level, and each triplicated LUTs are voted by a voter built by the abundant tristate buffer (BUFT) resources in Virtex FPGAs, hence no area overhead will be brought in by voter insertion. Experiments on MCNC’91 benchmarks show that our method can reduce about 30% area overhe