Arria10JESD204BAD9144-AD9625分析.PDFVIP

Arria 10 JESD204B AD9144-AD9625 Interoperability Reference Design User Guide Date: 2015 October 2 Revision: 1.0 ©2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at /common/legal.html. Altera warrants performance of its semiconductor products to current specifications in accordance with Alteras standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. Table of Contents Overview 3 Theory of Operation 3 Software Requirements 5 Hardware Setup 5 Quick Start Guide 8 Design Regeneration 12 List of Figures Figure 1: Reference Design Simplified Block Diagram 5 Figure 2: FMC port A and B adjustable voltage jumper settings 7 Figure 3: Hardware setup for TX-only operation with AD9144 EVM 7 Figure 4: Hardware setup for TX and RX operation with AD9144 and AD9625 EVM 8 Figure 5: X3 clock source setup 8 Figure 6: Run the reference design from NIOS II command shell 9 Figure 7: Identify JTAG cable number from Windows command prompt 9 Figure 8: Observing sine wave at oscilloscope 10 Figure 9: Messages printed at the NIOS II command shell 11 Figure 10: Move up the QSYS hierarchy 13 2 Overview This