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Power Efficient Resource Scaling in Partitioned Architectures through Dynamic Heterogeneity Naveen Muralimanohar, Karthik Ramani, Rajeev Balasubramonian School of Computing, University of Utah naveen, karthikr, rajeev@ Abstract provements do not translate into significant performance improvements. Long latencies can be tolerated effectively The ever increasing demand for high clock speeds and via a number of strategies, such as out-of-order execution the desire to exploit abundant transistor budgets have re- with a large in-flight instruction window, data prefetching, sulted in alarming increases in pr ocessor power dissipa- etc. However, the quest for instruction-level parallelism tion. Partitioned (or clustered) architectures have beenpr o- (ILP) often succumbs to the law of diminishing returns. posed in recent years to address scalability concerns infu- Once the low-hanging fruit has been picked, transistors al- ture billion-transistor microprocessors. Our analysis shows located for ILP yield marginal improvements, but expend that increasing pr ocessor resources in a clustered archi- significant energy. This paper investigates if abundant tran- tecture results in a linear increase in power consumption, sistor budgets can be exploited without causing inordinate while pr oviding diminishing improvements in single-thread increases in power density. performance . To pr eserve high performance to power ra- Partitioned architectures [2, 6, 7, 12, 20] have been pro- tios, we claim that the power consumption of additional