arm课堂笔记（国外英文资料）.docVIP

arm课堂笔记（国外英文资料） Register: storage unit that temporarily stores the results of alu R0 ~ r7 a set of 8 kinds of model utility a group of eight The r8 ~ r12 2 group of fiq private groups, the remaining 7 models share a set of 5 * 2 The R13 7 groups usr and system share one group, each of which is privately owned by a group of 7 The R14 group usr and system share one group, each of which is privately owned by a group of 7 R15 1 set of 8 kinds of model utility group 1 CPSR 1 set of 8 kinds of model utility group 1 The SPSR 6 group except system and usr, each of which has a private set of 6 How many registers are in the cortex-a core: 40 registers Questions about access to the register of the same name: Currently in usr mode Mov r0, sp (usr) Switching mode to fiq Mov r0, sp (fiq) Switching mode to the irq Mov r0, sp (irq) Switching mode to abort Mov r0, sp (abort) To undef switching mode Mov r0, sp (undef) Exception handling: PC - lr_mode PC - exception vector CPSR - spsr_mode CPSR -t = 0; J = 0, enter ARM state I, F if you need to be able to forbid it MODE [4:0] = MODE Four big steps for exception handling Now, when irq interrupts, PC - lr_irq PC = 0 x18 CPSR - spsr_irq CPSR -t = 0, J = 0; I, F Mode [Wednesday] = 10010 The suffix name of the ARm processor T: thumb instruction set support D: the debugging capability of mount debug M: 64 bit long multiplication I: embedded ICE is used to debug the CPU S: the abbreviation of TDMI E: supports DSP instructions J: Java bytecode support F: hardware floating point support 0 x8000 mov 0 x8004 sub 0 x8008 add 0 x800c and The relationship between the oc and the Fetch The Fetch = * PC First cycle: PC = 0 x8000 F: mov D: x E: x Second period: PC = 0 x8004 F: sub D: mov E: x Third cycle: PC = 0 x8008 F: add 0x8008 D: sub E: mov 0x8000 Fourth period: PC = 0 x800c F: and 0x800c D: the add E: sub 0x8004 An example of the LDR assembly line M W is the subunit of E Branch line example First cycle: PC = 0 x8008 F: ORR D: sub E: bl 0 x