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Encoder ±à???÷￡o LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY encoder IS PORT ) switch:in std_logic_vector(9 downto 0); reg_out:out std_logic; bcd_out:out std_logic_vector(3 downto 0) ;( end encoder; architecture behave of encoder is signal bcd_out1:std_logic_vector(3 downto 0); begin process(switch) begin if(switch(9)=1) then bcd_out=1001;reg_out=1; elsif(switch(8)=1) then bcd_out=1000;reg_out=1; elsif(switch(7)=1) then bcd_out=0111;reg_out=1; elsif(switch(6)=1) then bcd_out=0110;reg_out=1; elsif(switch(5)=1) then bcd_out=0101;reg_out=1; elsif(switch(4)=1) then bcd_out=0100;reg_out=1; elsif(switch(3)=1) then bcd_out=0011;reg_out=1; elsif(switch(2)=1) then bcd_out=0010;reg_out=1; elsif(switch(1)=1) then bcd_out=0001;reg_out=1; elsif(switch(0)=1) then bcd_out=0000;reg_out=1; else bcd_out=0000;reg_out=0; end if; end process; end behave; Register ??′??÷ A￡o library ieee; USE IEEE.STD_LOGIC_1164.ALL; ENTITY REG_A IS PORT(clk:in STD_LOGIC; DIN:IN STD_LOGIC_VECTOR(3 downto 0); DOUT:OUT STD_LOGIC_VECTOR(7 downto 0)); END REG_A; ARCHITECTURE behave OF REG_A IS signal DOUT1:STD_LOGIC_VECTOR(7 downto 0); BEGIN PROCESS(clk) BEGIN if clkevent and clk=1 then dout1(7 downto 4)=dout1(3 downto 0); dout1(3 downto 0)=din; end if; END PROCESS; dout=dout1; END behave; ?aá??eμ?????μ?×÷ó?￡??ò??′óía??òyè?ò????????a1?￡?μ±?a1??a??off?ˉê±￡? ??′??÷ A 1¤×÷￡???êy?÷￡¨?????á?2μ?￡?ò??±?????ˉ?￠?ˉ?￠ ?ˉ￡?±íê??°μúò????￠μúò????￠á?á￡?±￡??aê±μ??·′|óúò??·êy????????×′ ì?￡???êyμ??·2?1¤×÷?￡μ±éè?¨o?ò???êyoó￡?′ò?a?a1?￡??aê±±à??μ??·2??ù1¤×÷￡? ò?????′??÷ A ?aò??±±￡3??ú???°éè?¨μ???×′ì?￡?êy??1üò2?áò??±??ê?éè?¨μ?êy ×??￡í?ê±?aê?×°ò?oí×°??￡???êyμ??·ò2?aê???êy1¤×÷?￡í?ê±￡?μ±??êy?úê±￡??á2ú éúò????ˉ??D?o?￡?ê1??êy?÷í￡?11¤×÷￡??a??D?o?μ?ó??è????óú?????a1??￡ Source Procedure of each module(????μ￥?a?′3ìDò) library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all; use ieee.std_logic_arith.all; entity control is port(enable:in std_logic; warn:in std_logic; clear_coun