IC设计和版图中噪声减小的方法以及floorplan注意事项2.pdfVIP

Noise Reduction Is Crucial To Mixed-Signal ASIC Design Success (Part II) Floorplanning, I/O placement, pinout, and power-stability issues round out the noise- reduction design problem. by Jerry Twomey IBM MICROELECTRONICS Large CMOS ASICs and system-on-a-chip designs often contain both analog and digital sections. Combining the two into a mixed-signal IC frequently leads to noise problems. This article, the second in a two-part series, deals with noise-reduction matters affecting the whole IC. As discussed in the first article, engineers should think about addressing noise issues as part of the design process to avoid such difficulties during chip debug [Noise Reduction Is Crucial To Mixed-Signal ASIC Design Success (Part I), electronic design, Oct. 30, p. 123]. Dealing with the trouble after the fact can be costly. Complicating the situation is the fact that Spice simulations often dont show many noise problems. Impedance of interconnects, adjacent device coupling, and substrate noise are usually not modeled accurately. Transition switching noise is an RF issue, with a very broad spectrum. At these frequencies, connection inductance and parasitic capacitance become significant factors. Noise coupling is often distributed, with multiple talkers and listeners. Most effective methods of noise reduction include suppression of talkers at the source and use of noise-immune listeners throughout the IC. For our purposes, noise reduction refers to both reducing noise sources and using circuits and layouts that make the system less sensitive to noise. Note that including noise immunity in a design doesnt mean larger chips. Done properly, the die area usually doesnt change. Noise-Reduction Methods Noise-reduction methods can be categorized into four areas: providing low impedance and quiet connections for power, ground, and substrate; designing analog circuits that are less sensitive to noise; reducing or silencing any noise generators; and separ