南京大学09年计算机组织结构期中考试试题.docVIP

Computer organization and architecture Midterm exam 2010/11 I. Multi-choice Erasure unit for flash memory is ( B ) a. Chip level b. byte level c. block level d. word level Cache usually adopts ( B ) a. Direct access method (semi sequential) b. random access method c. Sequential access method d. read only method If memory cycle is 250ns and 16 bits are read each time, then the data transfer rate of the memory is ( d ) a. 4x106 bytes/s b. 4M bytes/s c. 8x106 bytes/s d. 8M bytes/s 4. 假设某系统总线在一个总线周期中并行传输4字节信息, 一个总线周期占用2个时钟周期, 总线时钟频率为10MHz, 则总线带宽是（ b ） a. 10 MB/s b. 20 MB/s c. 40 MB/s d. 80 MB/s 5. 浮点数加、减运算过程包括对阶、尾数运算、规格化、舍入和判溢出等步骤。设浮点数的阶码和尾数均采用补码表示，且位数分别为5位和7位（均含2位符号位）。若有两个数X=27x29/32，Y=25x5/8，则用浮点加法计算X+Y的最终结果是（ d ） a. 00111 1100010 b. 00111 0100010 c. 01000 0010001 d. 发生溢出 6. 设某浮点数共12位, 其中阶码含1位阶符共4位, 以2为底, 补码表示; 尾数含1位数符共8位, 补码表示, 规格化。则该浮点数所能表示的最大正数是（ ）。 a. 27 b. 28 c. 28-1 d. 27-1 7. 不恢复余数除法（也称加减交替除法）C a. 不存在恢复余数的操作 b. 当某一步运算不够减时，做恢复余数操作 c. 仅当最后一步余数为负时，做恢复余数操作 d. 当某一步余数为负时，做恢复余数操作 8. 指令周期是指CPU从主存取出一条指令的时间? CPU执行一条指令的时间 CPU从主存取出一条指令加上执行一条指令的时间??? 时钟周期时间 and 1004. Note: instructions are two addresses one. “Load $R1, 1006” register R1? (1006) “Add $R2, $R1” $R2 ? ($R1) + ($R2) “ISZ $R1” increment $R1, if $R1 is zero then jump to 1005 else do 1004 “BR 1002” branch 1002 Memory CPU 1000 Load $R1, 1006 PC 1002 1001 Clear $R2 1002 Add $R2, $R1 IR 1003 ISZ $R1 1004 BR 1002 R1 -5 1005 Store $R2, 1007 –5 R2 0 S Consider a hypothetical microprocessor generating a 16-bit address and having a 16-bit data bus. What is the maximum memory address space that the processor can access directly if it is connected to a “16-bit memory”? What is the maximum memory address space that the processor can access directly if it is connected to a “8-bit memory”? If an input and an output instruction can specify an 8-bit I/O port number, how many 8-bit I/O ports can the microprocessor support? H