74ACT245_DataSheet.pdfVIP

1/9April 2001 ■ HIGH SPEED: t PD = 5.4ns (TYP.) at V CC = 5V ■ LOW POWER DISSIPATION: I CC = 4 μA(MAX.) at T A =25°C ■ COMPATIBLE WITH TTL OUTPUTS V IH = 2V (MIN.), V IL = 0.8V (MAX.) ■ 50? TRANSMISSION LINE DRIVING CAPABILITY ■ SYMMETRICAL OUTPUT IMPEDANCE: |I OH | = I OL = 24mA (MIN) ■ BALANCED PROPAGATION DELAYS: t PLH ? t PHL ■ OPERATING VOLTAGE RANGE: V CC (OPR) = 4.5V to 5.5V ■ PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 245 ■ IMPROVED LATCH-UP IMMUNITY DESCRIPTION The 74ACT245 is an advanced high-speed CMOS OCTAL BUS TRANSCEIVER (3-STATE) fabricated with sub-micron silicon gate and double-layer metal wiring C 2 MOS tecnology. This IC is intended for two-way asynchronous communication between data buses and the direction of data transmission is determined by DIR input. The enable input G can be used to disable the device so that the buses are effectively isolated. The device is designed to interface directly High Speed CMOS systems with TTL, NMOS and CMOS output voltage levels. All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage. IT IS PROHIBITED TO APPLY A SIGNAL TO A TERMINAL WHEN IT IS IN OUTPUT MODE AND WHEN A BUS THERMINAL IS FLOATING (HIGH IMPEDANCE STATE) IT IS REQUIRED TO FIX THE INPUT LEVEL BY MEANS OF EXTERNAL PULL DOWN OR PULL UP RESISTOR. 74ACT245 OCTAL BUS TRANSCEIVER WITH 3 STATE OUTPUTS (NON INVERTED) PIN CONNECTION AND IEC LOGIC SYMBOLS ORDER CODES PACKAGE TUBE T R DIP 74ACT245B SOP 74ACT245M 74ACT245MTR TSSOP 74ACT245TTR TSSOPDIP SOP 74ACT245 2/9 INPUT AND OUTPUT EQUIVALENT CIRCUIT PIN DESCRIPTION TRUTH TABLE X : Don’t Care Z : High Impedance ABSOLUTE MAXIMUM RATINGS Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. RECOMMENDED OPERATING CONDITIONS 1) V IN from 0.8V to 2.0V PIN No SYMBOL NAME AND FUNCTION 1 DIR D