ANewModelforTimingJitter.PDFVIP

A New Model for Timing Jitter Caused by Device Noise in Current-Mode Logic Frequency Dividers Marko Aleksic, Nikola Nedovic*, K. Wayne Current, and Vojin G. Oklobdzija Department of Electrical and Computer Engineering, University of California, Davis, CA 95616 maleksic@ucdavis.edu Abstract. A new method for predicting timing jitter caused by device noise in current-mode logic (CML) frequency dividers is presented. Device noise trans- formation into jitter is modeled as a linear time-varying (LTV) process, as op- posed to a previously published method, which models jitter generation as a lin- ear time-invariant (LTI) process. Predictions obtained using the LTV method match jitter values obtained through exhaustive simulation with an error of up to 7.7 %, whereas errors of the jitter predicted by the LTI method exceed 57 %. 1 Introduction Timing jitter (or phase noise, if observed in the frequency domain) is a major con- straint in modern high-speed communication systems. Jitter imposes limitations to the maximum signaling rate for which the bit error rate (BER) does not exceed its maxi- mum acceptable level, the minimum spacing between channels in order to avoid inter- channel interference, etc. Unfortunately, jitter does not scale down with the signal period. As the signaling rates increase and are now in the range of tens of Gbps, even small amounts of jitter can severely impair the performance of these systems. It would be very desirable to know the amount of jitter that will be caused by de- vice noise of circuits in a system before the system is actually fabricated. This way, it would be possible to determine whether the system meets the requirements in the pre- fabrication phase of the design process, and hence, reduce the cost of the design. For that reason, a lot of research has been done on jitter and phase noise analysis of dif-