tangy_PLL_frequency_synthesizer.pdfVIP

Phase-Locked Loop Based Frequency Synthesizer for Wireless Communication Yiwu Tang Information Electronics Group March 9, 2000 Outline ? PLL frequency synthesizer fundamentals ? A design example – a 433MHz ISM frequency synthesizer ? Work going on and future work PLL Fundamentals (I) Basic Architecture Phase Frequency Detector Low Pass Filter VCO Programmable Frequency Divider /N ~ Fref RF Output Fo PLL Fundamentals (II) Key blocks in a PLL ? Phase frequency detector ? Charge pump and loop filter ? Voltage controlled oscillator (VCO) ? Frequency divider – Prescaler – Program counter – swallow counter PLL Fundamentals (III) Major Design Issues ? Performance specification – Dynamic performance: lock range, lock time… – Noise performance: phase noise, time jitter… ? Design considerations – Performance of each building block – Simulation at different levels for entire loop ? Implementation in CMOS Design Example (I) Overall Architecture A 433MHz CMOS Frequency Synthesizer Frequency/ Phase Detector Charge Pump VCO Frequency Divider /200 5.16MHz Reference Generation LO frequency Selection Prescalar /7, /8 Program Counter /2400 Swallow Counter /3, /4, /5 433, 432.974, 433.026 MHz Loop Filter On-chip Components Up Down ? Frequencies generated: 433MHz, 433MHz±26kHz ? Reference frequency: 26kHz ? Frequency divide ratio: 16803, 16804, 16805 ? Prescaler: 7, 8 Program counter: 2400 Swallow counter: 3, 4, 5 Design Example (II) Phase Frequency Detector Q Q SET CLR D Q Q SET CLR D Up DOWN Vcc Vcc Fdiv Fref Design Example (III) Charge Pump and Loop Filter Up Down /Up /Down Bias circuit Wide swingcurrent source (NMOS, discharge) Wide swing current source (PMOS, charge) 2nd order loop filter Design Example (III) Charge Pump and Loop Filter 0 0.5 1 1.5 2 x 10-5 0 1 2 3 Time (s ) U P s ig na l (V ) 0 0.5 1 1.5 2 x 10-5 0 1 2 3 Time (s ) D O W N s ig na l (V ) 0 0.5 1 1.5 2 x 10-5 0 1 2 3 Time (s ) V C O c on tro l s ig na l (V ) Design Example (IV) Prescaler Q Q SET