An improved frequency compensation tech for CMOS OpAmps 1983.pdfVIP

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An improved frequency compensation tech for CMOS OpAmps 1983.pdf

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An improved frequency compensation tech for CMOS OpAmps 1983

IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. SC-18,NO. 6, DECEMBER 1983 629 ACKNOWLEDGMENT The authors gratefully acknowledge the contributions of C. Laber to the design of the presented power amplifier. [1] [2] W. C. Black, Jr., D. J, Allsto~, and R. A. Reed, “A high performance low power CMOS channel falter,” IEEE J. Solid-State Circuits,vol. SC-15, pp. 921-929, Dec. 1980, D, Senderowicz, D. Hodges, and P, Gray, “High-performance NMOS operational amplifier,” IEEE J. So[id-StateCircuits,vol. SC-13, pp. 760-766, Dec. 1978. Kevin E. Brefnner (S’79-M80) received the B.S.E.E. degree from the University of Michigan, Ann Arbor, in 1980 and is currently working on the M.S.E.E. at the University of Santa Clara, Santa Clara, CA. From 1980 to 1981 he was a Design Engineer involved in subscriber ?Wy# loop products for the Telecommunications Group at Mostek, Carrollton, TX. In 1981 he joined the ‘*$ Telecom Group at Nationaf Semiconductor, qx Santa Clara, CA, as a Design Engineer, where he . . is involved in CMOS anrdog circuit design. ~ An Improved Frequency Compensation Technique for CMOS Operational Amplifiers BHUPENDRA K. AHUJA Mstract —The commonly used two-stage CMOS operational amplifier suffers from two basic performance limitations due to the RC compensa- tion network around the second gain stage. First, this frequency compensa- tion techrdque provides stable operation for limited range of capacitive loads, and second, the power supply rejection shows severe degradation above the open-loop pole frequency. The technique described here provides stable operation for a much larger range of capacitive loads, as well as much improved V8B power supply rejection over very wide bandwidths for the same basic op amp circuit. This paper presents mathematical analysis of this new technique in terms of its frequency and noise characteristics followed by its implementation in all n-well CMOS process. Experimental results show 70 dB negative power supply rejection at 100 kHz and an inp