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2003 Noise Model of Gate-Leakage Current in Ultrathin Oxide MOSFETs.pdf

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2003 Noise Model of Gate-Leakage Current in Ultrathin Oxide MOSFETs

IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 50, NO. 12, DECEMBER 2003 2499 Noise Model of Gate-Leakage Current in Ultrathin Oxide MOSFETs Jonghwan Lee, Gijs Bosman, Senior Member, IEEE, Keith R. Green, Member, IEEE, and D. Ladwig Abstract—A physics-based analytical model of the gate-leakage current noise in ultrathin gate oxide MOSFETs is presented. The noise model is based on an inelastic trap-assisted tunneling transport. We employ the barrier height fluctuation model and the Lorentzian-modulated shot noise of the gate-leakage current stemming from the two-dimensional electron gas channel to explain the excess noise behavior. The excess noise can be inter- preted as the sum of 1 noise and the Lorentzian-modulated shot noise. Trap-related processes are the most likely cause of excess current noise because slow traps in the oxide can result in low-frequency dissipation in the conductance of oxides and fast traps can produce the Lorentzian-modulated shot noise associated with generation-recombination process at higher frequencies. In order to verify the proposed noise model, the simulation results are compared with experimental data, and excellent agreement is observed. Index Terms—1 noise, barrier height fluctuation, gate- leakage current, generation–recombination (G–R) noise, inelastic trap-assisted tunneling (ITAT), Lorentzian-modulated shot noise. I. INTRODUCTION O NE OF THE important problems associated with the downscaling of CMOS technologies is an increase in the importance of random noise, which is always a practical limit to the performance of a device [1], [2]. As a result, the signal-to-noise ratio of analog circuits is reduced, and bit errors occur in data transmission systems. The scaling of device dimensions, resulting in the use of thinner oxide layers, is especially necessary for enhancing circuit speed at low voltages, providing the same capacitance within a smaller area, and offering lower programming voltages for nonvolatile memory. However, the c