AD9201数据手册.pdfVIP

AD9201 One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: Fax: 781/326-8703 ? Analog Devices, Inc., 1999 REV. D Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. a Dual Channel, 20 MHz 10-BitResolution CMOS ADC FEATURES Complete Dual Matching ADCs Low Power Dissipation: 215 mW (+3 V Supply) Single Supply: 2.7 V to 5.5 V Differential Nonlinearity Error: 0.4 LSB On-Chip Analog Input Buffers On-Chip Reference Signal-to-Noise Ratio: 57.8 dB Over Nine Effective Bits Spurious-Free Dynamic Range: –73 dB No Missing Codes Guaranteed 28-Lead SSOP FUNCTIONAL BLOCK DIAGRAM 1V REFERENCE BUFFER QREFB IREFB QREFT IREFT VREF REFSENSE IINA IINB I ADC QINB QINA Q ADC Q REGISTER I REGISTER THREE- STATE OUTPUT BUFFER AVDD AVSS CLOCK DVDD DVSS SLEEP SELECT DATA 10 BITS CHIP SELECT AD9201 ASYNCHRONOUS MULTIPLEXER PRODUCT DESCRIPTION The AD9201 is a complete dual channel, 20 MSPS, 10-bit CMOS ADC. The AD9201 is optimized specifically for applica- tions where close matching between two ADCs is required (e.g., I/Q channels in communications applications). The 20 MHz sampling rate and wide input bandwidth will cover both narrow- band and spread-spectrum channels. The AD9201 integrates two 10-bit, 20 MSPS ADCs, two input buffer amplifiers, an internal voltage reference and multiplexed digital output buffers. Each ADC incorporates a simultaneous sampling sample-and- hold amplifier at its input. The analog inputs are buffered; no external input buffer op amp will be required in most applica- tions. The ADCs are implemented using a multistage pipeline architecture that offers accurate performance and guarantees no missing codes. The outputs o