Adaptive Debug and Diagnosis Without Fault Dictionaries.pdfVIP

Adaptive Debug and Diagnosis Without Fault Dictionaries Stefan Holst, Hans-Joachim Wunderlich Institut fu?r Technische Informatik Universita?t Stuttgart Pfaffenwaldring 47; D-70569 Stuttgart, Germany email: {holst, wu}@informatik.uni-stuttgart.de Abstract—Diagnosis is essential in modern chip production to increase yield, and debug constitutes a major part in the pre- silicon development process. For recent process technologies, defect mechanisms are increasingly complex, and continuous efforts are made to model these defects by using sophisticated fault models. Traditional static approaches for debug and diagnosis with a simplified fault model are more and more limited. In this paper, a method is presented, which identifies pos- sible faulty regions in a combinational circuit, based on its input/output behavior and independent of a fault model. The new adaptive, statistical approach combines a flexible and powerful effect-cause pattern analysis algorithm with high- resolution ATPG. We show the effectiveness of the approach through experiments with benchmark and industrial circuits. Keywords—Diagnosis, Debug, Test, VLSI I. INTRODUCTION A. Debug and diagnosis Traditionally, design, verification and diagnosis of micro- electronic circuits have been viewed as separate tasks with individual challenges and techniques. However, in recent years more and more attention has been paid to the inter- action of individual design steps in verification, diagnosis of prototypes, and field return analysis. These are tasks for quality control and improvement during the complete lifecycle of the system by tackling faults occurring during design, manufacturing and operation. Debug is the time-consuming task of identifying faulty modules and structures within the design. While some methods of formal verification are constructive and able to find the cause of malfunctions, simulation and emulation usually require additional efforts for fault location. As Systems on Chip (SoC) design comp