fpga第六章_Verilog_HDL高级设计举例教案.ppt

* * Microelectronics School Xidian University wire [DATA_WIDTH-1:0] x1,y1,z1; wire [DATA_WIDTH-1:0] x2,y2,z2; wire [DATA_WIDTH-1:0] x3,y3,z3; wire [DATA_WIDTH-1:0] x4,y4,z4; wire [DATA_WIDTH-1:0] x5,y5,z5; wire [DATA_WIDTH-1:0] x6,y6,z6; wire [DATA_WIDTH-1:0] x7,y7,z7; reg [1:0] quadrant[PIPELINE:0]; integer i; //get real quadrant and map to first quadrant always@(posedge clk or negedge rst_n) begin if(!rst_n) phase_in_reg=8b0000_0000; else if(ena) begin case(phase_in[7:6]) 2b00:phase_in_reg=phase_in; 2b01:phase_in_reg=phase_in-8h40; //-pi/2 2b10:phase_in_reg=phase_in-8h80; //-pi * * Microelectronics School Xidian University 2b11:phase_in_reg=phase_in-8hc0; //-3pi/2 default:; endcase end end //define initial constant x=0.60725,y=0; always@(posedge clk or negedge rst_n) begin if(!rst_n) begin x0=8b0000_0000; y0=8b0000_0000; z0=8b0000_0000; end else if(ena) begin x0=8h4D; y0=8h00; z0=phase_in_reg; end end * * Microelectronics School Xidian University lteration #(8,0,8h20)u1(.clk(clk),.rst_n(rst_n),.ena(ena), .x0(x0),.y0(y0),.z0(z0),.x1(x1),.y1(y1),.z1(z1)); lteration #(8,1,8h12)u2(.clk(clk),.rst_n(rst_n),.ena(ena), .x0(x1),.y0(y1),.z0(z1),.x1(x2),.y1(y2),.z1(z2)); lteration #(8,2,8h09)u3(.clk(clk),.rst_n(rst_n),.ena(ena), .x0(x2),.y0(y2),.z0(z2),.x1(x3),.y1(y3),.z1(z3)); lteration #(8,3,8h04)u4(.clk(clk),.rst_n(rst_n),.ena(ena), .x0(x3),.y0(y3),.z0(z3),.x1(x4),.y1(y4),.z1(z4)); lteration #(8,4,8h02)u5(.clk(clk),.rst_n(rst_n),.ena(ena),