20080625_understand_testbench_pc2.pptVIP

Testbench architecture FPGA functions FPGA function to be simulated ISPB? OK access to internal registers access to EB2 bus (using also a model for switch EB2 interface) GMII? OK for V0 ? all packets are looped back for future versions ? you will have to generate EPS packets, sync packets, tdm packets (loop-back packets) RGMII? OK SGMII? OK ALARM? OK PM COUNTERS DDR MEMORY CLOCKS If the FPGA design is not finished, for example, some blocks are not designed, what should the FPGA be look like? As to run the simulation, should I set the unused signals to fixed values? Yes, you can fix input signals because you do not care the FPGA on the test bench is ANYWAY the whole FPGA If there’s no model for test, what should the test-bench be look like? Set it to fixed value? NO, the risk is that you simulate something that is very far from reality ? you just waste your time because you cannot put on board a tested feature Write a model, don’t care the function? YES. Write a model but caring of the function; at least (as for EB2 case) you have to reproduce in simulation the timing of the interfaces it is not easy to give general rules; we have to see case by case; we have to find the good trade off between complexity of model and effort to develop it Unfortunately it is case by case each time = for example for the EB2, the best is to reproduce the timing of the interface and to implement a little memory in this bloc to make several read/write access like a memory model functions model function DDR Model OK SWITCH_EB2 interface OK …… I do not see today the need for other models (the only one could be the switch for something like loop-back, but it would not be a real model of the component, just loop-back!) If there’s no model for test, what should the test-bench be look like? Set it to fixed value? Write a model, don’t care the function? (Do not know it is OK?) Write a model, according to the datasheet? (spend more time!! And do not know it is OK?) YES, I think this is the c