ECE 260B CSE241A VLSI Digital CircuitsECE 260B cse241a VLSI数字电路.pptVIP

ECE260B – CSE241AWinter 2005Power Distribution Motivation Power supply noise is a serious issue in DSM design Noise is getting worse as technology scales Noise margin decreases as supply voltage scales Power supply noise may slow down circuit performance Power supply noise may cause logic failures Power = … Routing resources 20-40% of all metal tracks used by Vcc, Vss Increased power ? denser power grid Pins Vcc or Vss pin carries 0.5-1W of power Pentium 4 uses 423 pins; 223 Vcc or Vss More pins ? package more expensive (+ package development, motherboard redesign, …) Battery cost 1kg NiCad battery powers a Pentium 4 alone for less than 1 hour Performance High chip temperatures degrade circuit performance Large across-chip temperature variations induce clock skew High chip power limits use of high-performance circuits Power transients determine minimum power supply voltage Power = Package Planning for Power Early simulation of major power dissipation components Early quantification of chip power Total chip power Maximum power density Total chip power fluctuations inherent added fluctuations due to clock gating Early power distribution analysis (dc, ac, multi-cycle) I.e., average, maximum, multi-cycle fluctuations Early allocation coordination of chip resources Wiring tracks for power grid Low Vt devices Dynamic circuits Clock gating Placement and quantity of added decoupling capacitors Power and Ground Routing Floorplanning includes planning how the power, ground and clock should route Power supply distribution Tree: trunk must supply current to all branches Resistance must be very small since when a gate switches, its current flows through the supply lines If the resistance of supply lines is too large, voltage supplied to gates will drop, which can cause the gate to malfunction Usually, want at most 5-10% IR drop due to supply resistance ? Usually on the top layers of metal, then distributed to lower wirin