LCD计数显示程序.docVIP

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity counter is Port ( clk : in std_logic; resetn : in std_logic; dout : out std_logic_vector(7 downto 0); lcd_en : out std_logic; lcd_rs : out std_logic; lcd_rw : out std_logic); end counter; architecture Behavioral of counter is component counter60 is Port ( clk : in std_logic; resetn : in std_logic; dout : out std_logic_vector(7 downto 0)); end component; component decoder is Port (din:in std_logic_vector(3 downto 0 ); dout:out std_logic_vector(8 downto 0) ); end component; component lcd_interface is port ( clk : in std_logic; resetn : in std_logic; dout_s10 : in std_logic_vector (8 downto 0); dout_s1 : in std_logic_vector (8 downto 0); lcd_data : out std_logic_vector (7 downto 0); lcd_en : out std_logic; lcd_rs : out std_logic; lcd_rw : out std_logic ); end component; signal ddout_s10 : std_logic_vector (8 downto 0); signal ddout_s1 : std_logic_vector (8 downto 0); signal ddout : std_logic_vector (7downto 0); begin u1: counter60 port map(clk,resetn,ddout); u2: decoder port map(ddout(7 downto 4),ddout_s10); u3: decoder port map(ddout(3 downto 0),ddout_s1); u4: lcd_interface port map(clk,resetn, ddout_s10,ddout_s1,dout,lcd_en, lcd_rs , lcd_rw); end Behavioral; -------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 13:36:10 03/30/06 -- Design Name: -- Module Name: count60 - Behavioral -- Project