HDL七段译码器.docxVIP

　　 七段译码器详细设计方案 七段译码器简介： VHDL 与 Verilog 数码管的七段译码 七段译码规格： 四输入的七段译码器 实现原理 真值表 引脚 HDL源代码 Verilog HDL代码为： module vr7seg( input[3:0] d , output[7:0] q ); reg[7:0] q_r; always @(d) begin case(d) 4h0 : q_r = 8hC0; 4h1 : q_r = 8hF9; 4h2 : q_r = 8hA4; 4h3 : q_r = 8hB0; 4h4 : q_r = 8h99; 4h5 : q_r = 8h92; 4h6 : q_r = 8h82; 4h7 : q_r = 8hF8; 4h8 : q_r = 8h80; 4h9 : q_r = 8h90; 4hA : q_r = 8h88; 4hB : q_r = 8h83; 4hC : q_r = 8hC6; 4hD : q_r = 8hA1; 4hE : q_r = 8h86; 4hF : q_r = 8h8E; default : q_r = 8hFF; endcase end assign q = q_r; endmodule VHDL代码为 代码一： library ieee ; use ieee.std_logic_1164.all ; entity vr7seg is port ( d : in std_logic_vector(3 downto 0); q : out std_logic_vector(7 downto 0) ) ; end vr7seg ; architecture arch_vr7seg of vr7seg is begin process(d) begin case d is when x0 = q = xC0; when x1 = q = xF9; when x2 = q = xA4; when x3 = q = xB0; when x4 = q = x99; when x5 = q = x92; when x6 = q = x82; when x7 = q = xF8; when x8 = q = x80; when x9 = q = x90; when xA = q = x88; when xB = q = x83; when xC = q = xC6; when xD = q = xA1; when xE = q = x86; when xF = q = x8E; when others = q = xFF; end case; end process; end arch_vr7seg ; 代码二： library ieee ; use ieee.std_logic_1164.all ; entity vr7seg is port ( d : in std_logic_vector(3 downto 0); q : out std_logic_vector(7 downto 0) ) ; end vr7seg ; architecture arch_vr7seg of vr7seg is begin q = xC0 when d=x0 else xF9 when d=x1 else xA4 when d=x2 else xB0 when d=x3 else x99 when d=x4 else x92 when d=x5 else x82 when d=x6 else xF8 when d=x7 else x80 when d=x8 else x90 when d=x9 else x88 when d=xA else x83 when d=xB else xC6 when d=xC else xA1 when d=xD else x86 when d=xE else x8E when d=xF else xFF ; end arch_vr7seg ; VHDL仿真代码： library ieee; use