锁相环原理以及倍频分频实现.docVIP

锁相环原理以及倍频/分频实现 A?phase-locked loop?(PLL) is a closed-loop frequency-control system based on the phase difference between the input clock signal and the feedback clock signal of a controlled oscillator. Figure 1 shows a simplified block diagram of the major components in a PLL. The main blocks of the PLL are the phase frequency detector (PFD), charge pump, loop filter, voltage controlled oscillator (VCO), and counters, such as a feedback counter (M), a pre-scale counter (N), and post-scale counters(C). 注.锁相环是一种基于输入信号与输入信号反馈给振荡控制器的信号之间的相位差的闭环频率控制系统.图1 展示了锁相环的基本原理框图。图中的PLL主要由鉴相器（PFD），电荷泵，回路滤波器，压控振荡电路（VCO）,计数器（反馈技术器M，预分频技术器N，后分频C）. Figure 1. Block Diagram of a PLL PLLs in Altera??FPGAs align the rising edge of the reference input clock to a feedback clock using the PFD. The falling edges are determined by the duty-cycle specified by the user. The PFD detects the difference in phase and frequency between the reference clock and feedback clock inputs and generates an “up” or “down” control signal based on whether the feedback frequency is lagging or leading the reference frequency. These “up” or “down” control signals determine whether the VCO needs to operate at a higher or lower frequency, respectively. 注.Altera FPFG 芯片内的PLL中,在每个参考时钟的上升沿将通过鉴相器(PFD) 产生一个反馈时钟信号.由用户指定的占空比来决定时钟的下降沿.PFD检测参考时钟与反馈时钟之间的频率差以及相位差并产生”up”或”down”的控制信号.这个控制信号表征着反馈信号是超前还是落后于参考时钟信号.这两种不同的信号决定着压控振荡器(VCO)是否需要提高频率或者降低频率. The PFD outputs these “up” and “down” signals to a charge pump. If the charge pump receives an up signal, current is driven into the loop filter. Conversely, if it receives a down signal, current is drawn from the loop filter. 注.PFD产生的”up”,’’down”将输出给电荷泵,如果电荷泵接收到的是”up”信号,电流将进入环路滤波.相反的将从环路滤波器中吸取电流. The loop filter converts these signals to a control voltage that is used to bias the VCO. Based on the control voltage, the VCO oscillates at a higher or lower frequency, which affects the phase and frequency of the feedback clock. If the PFD produces an up signal, then the VCO frequency increa