毕业论文（设计）基于Verilog HDL的闹钟设计说明书.docVIP

封面删除~你懂的 摘 要 随着微电子技术、计算机技术、半导体技术的发展，很多传统的数字门电路的设计已经被可编程逻辑器件替代。而对于传统的模拟控制技术，也被数字控制系统所取代。数字系统在各个领域显示出了无穷的魅力与优势，如今已经被广泛应用于实际工程中。本文利用Verilog HDL 语言自顶向下的设计方法设计多功能数字钟, 实现时、分、秒的计时和校时，以及整点报时和闹钟的功能。突出了其作为硬件描述语言的良好的可读性、可移植性和易理解等优点, 并通过ModelSim SE 6.5 完成综合、仿真。通过Verilog HDL语言完成数字钟的层次化设计。 关键词:数字电子时钟，有限状态机，功能仿真 Abstract As the microelectronics, computer technology, semiconductor technology, many traditional design of digital gate programmable logic device has been replaced. As for the traditional analog control, digital control systems have also been replaced. Digital systems in various fields has shown infinite charm and advantages, and now has been widely used in practical projects. In this paper, Verilog HDL, the design of top-down multi-functional digital clock designed to achieve the hours, minutes, seconds, time and school, as well as the whole point timekeeping and alarm functions. Highlighted as a hardware description language, good readability, portability and ease of understanding, etc., and through the ModelSim SE 6.5 complete the comprehensive, simulation. Completed by Verilog HDL, the level of the digital clock design. 朗读 显示对应的拉丁字符的拼音 ? 字典 Key words: Digital electronic clock, finite state machine, functional simulation 显示对应的拉丁字符的拼音 ? 字典  目 录 第1章 绪论......................................................................................................................................1 1.1时钟的发展简史..................................................................................................................1 1.2设计目的………………………………..............................................................................1 1.3Verilog HDL硬件描述语言.................................................................................................2 1.4Modelsim仿真工具.............................................................................................................5 第2章 数字电路设计方法..............................................................................................................7