FPGA-Based Hardware Acceleration of Lithographic Aerial Image.pdf

FPGA-Based Hardware Acceleration of Lithographic Aerial Image Simulation 17 JASON CONG and YI ZOU University of California, Los Angeles Lithography simulation, an essential step in design for manufacturability (DFM), is still far from computationally efficient. Most leading companies use large clusters of server computers to achieve acceptable turn-around time. Thus coprocessor acceleration is very attractive for obtaining increased computational performance with a reduced power consumption. This article describes the implementation of a customized accelerator on FPGA using a polygon-based simulation model. An application-specific memory partitioning scheme is designed to meet the bandwidth require- ments for a large number of processing elements. Deep loop pipelining and ping-pong buffer based function block pipelining are also implemented in our design. Initial results show a 15X speedup versus the software implementation running on a microprocessor, and more speedup is expected via further performance tuning. The implementation also leverages state-of-art C-to-RTL synthe- sis tools. At the same time, we also identify the need for manual architecture-level exploration for parallel implementations. Moreover, we implement the algorithm on NVIDIA GPUs using the CUDA programming environment, and provide some useful comparisons for different kinds of accelerators. Categories and Subject Descriptors: B.7.1 [Integrated Circuits]: Types and Design Styles— Algorithms implemented in hardware General Terms: Algorithms, Performance, Design Additional Key Words and Phrases: Lithography simulation, coprocessor acceleration, FPGA ACM Reference Format: Cong, J. and Zou, Y. 2009. FPGA-based hardware acceleration of lithographic aerial image simulation. ACM Trans. Reconfig. Techn. Sys