AM26LS32.pdfVIP

Order this document by AM26LS32/D           QUAD EIA–422/3 LINE Motorola′s Quad EIA–422/3 Receiver features four independent receiver RECEIVER WITH chains which comply with EIA Standards for the Electrical Characteristics of Balanced/Unbalanced Voltage Digital Interface Circuits. Receiver outputs THREE–STATE OUTPUTS are 74LS compatible, three–state structures which are forced to a high SEMICONDUCTOR impedance state when Pin 4 is a Logic “0” and Pin 12 is a Logic “1.” A PNP device buffers each output control pin to assure minimum loading for either TECHNICAL DATA Logic “1” or Logic “0” inputs. In addition, each receiver chain has internal hysteresis circuitry to improve noise margin and discourage output instability for slowly changing input waveforms. A summary of AM26LS32 features include: D SUFFIX • Four Independent Receiver Chains PLASTIC PACKAGE CASE 751B • Three–State Outputs (SO–16) • High Impedance Output Control Inputs (PIA Compatible) • Internal Hysteresis – 30 mV (Typical) @ Zero Volts Common Mode • Fast P