SampleHold_PFD_and_LF_Discussion.pptVIP

Sample-Hold PFD and LF Discussion Yu Han, RFIC, Aug 13rd, 2007 Type I PLL Type II PLL Type I PLL Type II PLL Noise Analysis Total Phase Noise = Ni(ω)*|Hi(ω)|2 + Nvco(ω)*|Hvco(ω)|2 Hi(ω)=ωn2/(s2+2ξωns+ωn2) ---- Low pass filter Hvco(ω)= (s2+2ξωns)/(s2+2ξωns+ωn2) ---- High pass filter The tradeoff of In-band and VCO noise, ωp=ωref/10~ωref/20 Minimize Power/Ground noise Minimize Switch ON/OFF feedthrough in CP Spur Analysis Loop Filter Design Loop Filter Design PFD Design PFD Design ---- Modification 1 PFD Design ---- Modification 2 Test circuitry ---- Linearity Test circuitry ---- Close Loop Problems for discussion Problem about ξ ωp≈2.1M, Kpd=ILF/(2лCs)=75u/(2л*0.5p)≈23.87M, Kv=100M so ξ=[ωpN/(KpdKv)]0.5/2≈0.25*103 ----? ξ too small: not enough phase margin, PM≈100ξdeg serious jitter, because the control line is easy to oscillate. Solutions for discussion: Place Cs and Ch outside, to get small Kpd. Add zero to form type II PLL. Problems for discussion Thank You! * * ωn=(KpdKv/N)0.5 ξ=(KpdKv/N)0.5/(2ωz) ξωn=KpdKv /(2ωz) (ξ=0.707 — Best Butterworth Filter, ξ=0.5 — Minimum Noise Bandwidth) ωn=(ωpKpdKv/N)0.5 ξ=[ωpN/(KpdKv)]0.5/2 ξωn=ωp/2 ωn and ξ (Lock Time TL is proportional to ξωn) 0 ωi/(KpdKv) Static Phase Diff Close Loop Function (1+s/ωz)/s 1/(1+s/ωp) G(s) Type II Type I Yes (Inverse proportional toξ) Open Loop Baud Plot No (Due to no zero) Jitter Peaking (Close Loop Baud Plot) Type II Type I Am is the amplitude of periodical spur at VCO controlling line voltage. Because Kvco and ωref is definite in specification, we can only minimize Am. For fraction-N Type II CPPLL, there are three factors: Periodical divide-ratio change Leakage current in loop filter and charge-pump Mismatch in the charge-pump Up and Down current sources Sample status Hold status Switch-Capacitor circuit basic function: With k=Ch/Cs When ωfref, the -3dB pole is: ωp=fref/(k+1/2)=frefCs/(Ch+Cs/2) It is equalized to a RC-