数字集成电路综合及物理设计阶段的时序收敛方案.docVIP

  数字集成电路综合及物理设计阶段的时序 收敛方案# 谢扬，桑红石** 5 10 （华中科技大学,自动化学院,多谱信息处理技术国家级重点实验室，湖北 武汉 430074） 摘要：时序收敛是数字集成电路设计中最重要的任务之一。随着集成电路设计进入了深亚微 米时代，芯片规模不断增加，设计日趋复杂，时序收敛的难度也随之越来越大。本文基于图 像中低层处理 SoC 的综合乃至物理设计，着重讨论在此阶段使时序收敛的方法。本文首先 介绍 Design Compiler、IC Compiler 等 EDA 工具的时序分析方式，随后讨论如何利用工具对 设计设定合理的约束，最后介绍了各个阶段出现时序违例的解决方式。通过此方法最终使芯 片的时序达到收敛。 关键词：集成电路设计；时序；综合；物理设计 中图分类号：TN492 15 A Method to Achieve Timing Closure During Synthesis and Physical Design Stage of Digital Integrated Circuit Xie Yang, Sang Hongshi (National Key Labotayory of Science and Technology on Multi-spectral Information Processing, 20 25 30 35 40 School of Automation, Huazhong University of Science and Technology, Wuhan 437704, China) Abstract: In this paper,a method to achieve timing closure during synthesis and physical design stage of digita IC is discussed. Timing closure is one of the most important task in digital integrated circuit design. As integrated circuit develops into the deep sub-micron period, the size of chip and the complexity of design has increased significantly. As a consequence of this, it becomes more and more difficult to achieve timing closure. This paper has discussed the method to achieve timing closure in synthesis and physical design based on low-level image processing SoC design. This paper firstly introduces the way that Design Compiler and IC Compiler use to perform timing analysis, followed by a discussion of how to use the tool to set reasonable constraints on the design, and finally introduces the solutions to timing violations in various stages. This SoC has finally got timing closure by using this method.. Key words: integrated circuit; timing; synthesis; physical design 0 引言 时序是保证数字电路正确工作最关键的因素。随着集成电路制造工艺的进步，芯片设计 日趋复杂，为达成时序收敛，设计者也面临越来越大的挑战[1]。图像中低层处理 SoC 是本 实验室设计的一款 SoC。芯片采用 SMIC 0.18μm 工艺，最高时钟频率达到 100MHz。图像中 低层处理 SoC 的后端设计流程中，需要考虑时序收敛的包括综合、布局规划、时钟树综合、 布线等阶段，不同阶段有着不同的处理方式[2]。本文基于此 SoC 的设计过程，结合本人数 年来的数字集成电路设计经验，提出了一种数字集成电路设计中，综合以及布局布线阶段的 时序收敛方案。该方案首先对芯片做出合理而详尽的约束，包括综合阶段的严格约束、布局 布