基于DMA传输的高速采样系统设计.docVIP

基于DMA传输的高速采样 系统设计 基于DMA传输的高速采样 系统设计 Sampling based on high-speed DMA transfer System Design  摘 要 DMA技术是一种由DMA控制器完成的存储器与外部设备或存储器之间大数据量传输的方法。在DMA传输中，硬件设备代替CPU接管总线并负责数据传输，省去了由CPU负责传输时所必须的寻址指令。介绍了基于FPGA的数据的采集、基于NiosII进行DMA传输的过程和LCD上的显示。本课题通过采用FPGA内部软核NiosII通过DMA控制器实现采集模块的数据对串口缓冲区的直接传递，进而最大限度的减少CPU对采样，数据传递和串口发送的干预，从而使被采样数据以最大速率向上位机传递。具体应实现如下：设计硬件，实现FPGA与高速AD的硬件连接。使用硬件语言编写基于AD芯片时序的采样IP核，并使其具有Slave Avalon 总线流模式接口以便实现DMA数据读取。设计FIFO模块作为采样数据的缓冲区。在Altera中构建包含AD模块的NiosII系统。编写C语言，在NiosII系统中实现采样模块与串口传输之间的DMA传输通道，实现直接采样发生模式，并在LCD上进行显示状态。 关键词:DMA NiosⅡ系统 FPGA FIFO 直接采样 Abstract The DMA by the DMA controller technology is a complete memory and external devices or between the large amounts of data storage methods. In DMA transfer, the hardware device instead of CPU over the bus and is responsible for data transmission, eliminating the need for transmission by the CPU must be responsible for addressing instructions. Describes the FPGA-based data collection, based on the DMA transfer NiosII process and display on the LCD. The subject of internal soft-core by using FPGA through the DMA controllers NiosII data acquisition module is passed directly to the serial buffer, and then minimize the CPU on the sampling, data transmission and serial transmission of the intervention, so that the sampled data to the maximum Transfer rate of up crew. Concrete should achieve the following: design hardware, FPGA implementation of hardware and high-speed connections AD. Language use Vreilog AD chip timing of sampling based on IP core, and make it flow model with a Slave Avalon bus interface to implement DMA data read. FIFO module is designed as a sampled data buffer. Altera in the building included in the AD module NiosII system. write C language to implement the system in the NiosII sampling module and the DMA transfer between serial transmission channel, the direct sampling mode occurs, and the LCD display on the state. Key words : DMA NiosⅡ System FPGA FIFO Direct sampling 目 录 摘要 I Abstr