EDA课程设计报告书 数字信号之函数信号发生器.docVIP

EDA课程设计报告书 实验名称。 数字信号发生器 实验原理。 主要运用原理图输入设计方法。 实验目的 用EDA学到的知识自主设计一个可以输出4种不同波形的信号发生器。 4种波形分别为：正弦波，方波，锯齿波，三角波。 并加以控制其输出的波形：要求输出什么波形系统就控制输出什么波形。 实验程序。 1．6位计数器： LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY CNT6 IS PORT(clock:IN STD_LOGIC; Q:OUT STD_LOGIC_VECTOR(5 DOWNTO 0)); END; ARCHITECTURE one OF CNT6 IS SIGNAL Q1:STD_LOGIC_VECTOR(5 DOWNTO 0); BEGIN PROCESS(clock) BEGIN IF clockEVENT AND clock=1 THEN Q1=Q1+1; END IF; END PROCESS; Q=Q1; END one; 2．4选1选择器： LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY mux41a IS PORT(a,b:IN STD_LOGIC; A1,B1,C1,D1:IN STD_LOGIC_VECTOR(7 DOWNTO 0); outy:OUT STD_LOGIC_VECTOR(7 DOWNTO 0)); END; ARCHITECTURE one OF mux41a IS SIGNAL iny:STD_LOGIC_VECTOR(1 DOWNTO 0); BEGIN iny=ab; PROCESS(iny) BEGIN CASE iny IS WHEN 00 = outy = A1; WHEN 01 = outy = B1; WHEN 10 = outy = C1; WHEN 11 = outy = D1; END CASE; END PROCESS; END one; 3．正弦信号发生器： LIBRARY ieee; USE ieee.std_logic_1164.all; LIBRARY altera_mf; USE altera_mf.all; ENTITY sin_w IS PORT ( address : IN STD_LOGIC_VECTOR (5 DOWNTO 0); clock : IN STD_LOGIC ; q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0) ); END sin_w; ARCHITECTURE SYN OF sin_w IS SIGNAL sub_wire0 : STD_LOGIC_VECTOR (7 DOWNTO 0); COMPONENT altsyncram GENERIC ( address_aclr_a : STRING; init_file : STRING; intended_device_family : STRING; lpm_hint : STRING; lpm_type : STRING; numwords_a : NATURAL; operation_mode : STRING; outdata_aclr_a : STRING; outdata_reg_a : STRING; widthad_a : NATURAL; width_a : NATURAL; width_byteena_a : NATURAL ); PORT ( clock0 : IN STD_LOGIC ; address_a : IN STD_LOGIC_VECTOR (5 DOWNTO 0); q_a : OUT STD_LOGIC_VECTOR (7 DOWNTO 0) ); END COMPONENT; BEGIN q = sub_wire0(7 DOWNTO 0); altsyncram_component : altsyncram GENERIC MAP ( address_aclr_a = NONE, init_file = sine_w.hex, intended_device_family = Cyclone, lpm_hint =