自动化大二大三部分课设实验二课time.pdfVIP

libraryieee;

useieee.std_logic_1164.all;

useieee.std_logic_unsigned.all;

entitytimeis

port(sout,fout,hout,dout,mout,yout0:instd_logic;

k2,k3:instd_logic;

fin,hin,din,min,yin0,yin1,win:outstd_logic;

q:outstd_logic_vector(3downto0));

endtime;

architectureoneoftimeis

signalw:std_logic_vector(3downto0);

begin

process(k2,k3)

begin

ifk2eventandk2=1thenw=w+1;

ifw=8thenw=0000;

endif;

endif;

casewis

when

0000=fin=sout;hin=fout;din=hout;min=dout;yin0=mout;yin1=yout0;win

hout;

q=0000;

when

0001=fin=k3;hin=0;din=0;min=0;yin0=0;yin1=0;win=0;

q=0001;

when

0010=fin=0;hin=k3;din=0;min=0;yin0=0;yin1=0;win=0;

q=0010;

when

0011=fin=0;hin=0;din=0;min=0;yin0=0;yin1=0;win=k3;

q=0011;

when

0100=fin=0;hin=0;din=k3;min=0;yin0=0;yin1=0;win=0;

q=0100;

when

0101=fin=0;hin=0;din=0;min=k3;yin0=0;yin1=0;win=0;

q=0101;

when

0110=fin=0;hin=0;din=0;min=0;yin0=k3;yin1=0;win=0;

q=0110;

when

0111=fin=0;hin=0;din=0;min=0;yin0=0;yin1=k3;win=0;

q=0111;

when

1000=fin=0;hin=0;din=0;min=0;yin0=0;yin1=0;

q=1000;

whenothers=null;

endcase;

endprocess;

end;

库IEEE;使用IEEE.STD_LOGIC_1164.ALL;

使用IEEE.STD_LOGIC_UNSIGNED.ALL;

实体时间是端口（sout，fout，hout，dout，mout，yout0：instd_logic;

K2，K3：在std_logic中；

Fin，Hin，Din，Min，Yin0，Yin1，Win：Outstd_logic;

问：outstd_logic_vector（3降至0）;

结束时间；建筑的时间之一是信号W：std_logic_vector（3降至0）;

开始过程（K2，K3）开始如果k2event和k2=11，然后w=w+1;

如果w=8，则w