基于FPGA数字秒表设计实验报告.doc

电子科技大学 标 准 实 验 报 告 实验项目：基于FPGA数字秒表设计 目录 TOC \o 1-3 \h \u ; signal snext: STD_LOGIC_VECTOR(2 downto 0); Begin 为三八译码器置入使能信号 ncs = 0; 分频电路 process(clk) begin if rising_edge(clk) then if count = 47999 then count =(others=0); else count = count+1; end if; end if; end process; clk_1k = count(15); 同步计数电路 process(clk_1k,sreg(2)) begin if rising_edge(clk_1k) then if sreg(2) = 1 then z0=(others=0); z1=(others=0); z2=(others=0); z3=(others=0); z4=(others=0); z5=(others=0); z6=(others=0); elsif sreg(1) = 1 then z0 = z0+1; if z0 = 9 then z0 =(others=0); z1 = z1+1; if z1 = 9 then z1 =(others=0); z2 = z2+1; if z2 = 9 then z2 =(others=0); z3 = z3+1; if z3 = 9 then z3 = (others=0); z4 = z4+1; if z4 = 5 then z4 = (others=0); z5 = z5+1; if z5 = 9 then z5 = (others=0); z6 = z6+1; if z6 = 5 then z6 = (others=0); end if; end if; end if; end if; end if; end if; end if; end if; end if; end process; 扫描计数器 process(clk_1k) begin if rising_edge(clk_1k) then count_2 = count_2+1; end if; end process; s = count_2; 锁存器 process(sreg(0),z1,z2,z3,z4,z5,z6) begin if sreg(0) = 1 then q1 = z1; q2 = z2; q3 = z3; q4 = z4; q5 = z5; q6 = z6; end if; end process; process(count_2,q1,q2,q3,q4,q5,q6) begin case count_2 is when 000 = in_7 = q1; when 001 = in_7 = q2; when 011 = in_7 = q3; when 100 = in_7 = q4; when 110 = in_7 = q5; when = in_7 = q6; when others = in_7 = 1; end case; end process; 八段译码器 process(in_7) begin case in_7 is when 0000 = seg when 0001 = seg =10011; when 0010 = seg when 0011 = seg when 0100 = seg when 0101 = seg wh