基于VHDL的计时系统的设计_毕业设计论文.doc

PAGE IV PAGE III 基于VHDL的计时系统的设计 摘 要 本次设计是通过使用VHDL语言设计了一个综合的计时系统，能实现年、月、日、时、分、秒、星期的计数综合计时功能，同时将计时结果用15个七段数码管显示，并且可通过两个设置键对计时系统有关的参数进行调整。综合计时电路可分为计年电路、计月电路、计日电路、计时电路、计分电路、计秒电路、计星期电路等7个子模块，这7个子模块都具有预置、计数和进位功能。 关键词: VHDL；计时系统 Abstract Using the VHDL language design timing system ,a comprehensive system to achieve the year , month , day , hour ,minute and second weeks of counting and timing functions such as integrated , while timing the results of 15 seven-segment digital display ,and can be set by two key system parameters on the timing adjustment. Timing circuit integrated circuit can be divided into the seconds ,scoring circuit ,timing circuit, namely, on the circuit, monthly circuit, namely, 7-week circuit sub-module, which has a preset 7 sub-module, counting ,and carry function . Key words: VHDL；Timing system 目 录 摘要································································I Abstract····························································II 1 前言·····························································1 1.1 计时系统研究背景·············································1 1.2 设计要求·····················································1 1.3 设计方案与方案优点···········································2 1.4 设计的可行性·················································3 2 外围电路设计······················································4 2.1 电源设计······················································4 2.2 方波信号源设计···············································5 2.2.1晶振电路··················································5 2.2.2分频电路··················································6 2.3 七段数码显示电路·············································7 2.4 总体电路设计·················································9 3 VHDL内部电路设计···············································10 3．1 综合计时电路设计············································10 3.1.1 计秒电路设计············································10 3.1.2 计分电路设计············································12 3.1.3 计时电路设计····························