基于FPGA的学校打铃器设计毕业设计.docVIP

PAGE PAGE 基于FPGA的学校打铃器的设计 目 录 TOC \o 1-3 \h \z \u ; cnt0:=; elsif cpevent and cp=1 then if cnt1=0101 and cnt0=1000 then co=1; cnt0:=1001; elsif cnt01001 then cnt0:=cnt0+1; else cnt0:=; if cnt10101 then cnt1:=cnt1+1; else cnt1:=; co=0; end if; end if; end if; sqmsh=cnt1; sqmsl=cnt0; end process; end SEC; （2）分计数模块 library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity MINUTE is port(clk,clr:in std_logic; co:out std_logic; min1,min0:out std_logic_vector(3 downto 0) ); end MINUTE; architecture MIN of MINUTE is begin process(clk,clr) variable cnt1,cnt0:std_logic_vector(3 downto 0); begin if clkevent and clk=1 then if clr=1 then if cnt1=0101 and cnt0=1000 then co=1; cnt0:=1001; elsif cnt01001 then cnt0:=cnt0+1; else cnt0:=; if cnt10101 then cnt1:=cnt1+1; else cnt1:=; co=0; end if; end if; end if; end if; min1=cnt1; min0=cnt0; end process; end MIN; （3）时计数模块 library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity sh24 is port(clk:in std_logic; clr:in std_logic; sh:buffer std_logic_vector(3 downto 0); sl:buffer std_logic_vector(3 downto 0)); end sh24; architecture bhv of sh24 is begin process(clk,clr) begin if (clr=0)then sh=; sl=; elsif(clkevent and clk=1) then if(sh=0010and sl=0011)then sh=;sl=; else sl=sl+1; if(sl9)then sl=sl+1; else sl=; if(sh2)then sh=sh+1; else sh=; end if; end if; end if; end if; end process; end bhv; （4）调时模块 library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all; entity mux2to1 is port( key: in std_logic; a,b: in std_logic; c: out std_logic ); end mux2to1; architecture one of mux2to1 is begin process(key) begin if key=0then c=b; else c=a; end if; end process; end one; 4.闹钟模块 （1）定时模块 LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY ctrl_memo IS PORT( reset,k1,up_key: IN STD_LOGIC; --k1高电平为调时，低电平为调分 Q_hourb: OUT INTEGER RANGE 0 TO 9;--“时”高位 Q_houra : OUT INTEGER RANGE 0 TO 9;--“时”低位