CS61c ndash; Final ReviewFall 2004课件.ppt

VA - PA VM – Address Translation VPN used to index into page table and get Page Table Entry (PTE) PTE is located by indexing off of the Page Table Base Register, which is changed on context switches PTE contains valid bit, Physical Page Number (PPN), access rights VM – Translation Look-Aside Buffer (TLB) VM provides a lot of nice features, but requires several memory accesses for its indirection – this really kills performance The solution? Another level of indirection: the TLB Very small fully associative cache containing the most recently used mappings from VPN to PPN CPU Design – Steps to Design/Understand a CPU 1. Analyze instruction set architecture (ISA) = datapath requirements 2. Select set of datapath components and establish clocking methodology 3. Assemble datapath meeting requirements 4. Analyze implementation of each instruction to determine setting of control points. 5. Assemble the control logic Putting it All Together:A Single Cycle Datapath imm16 32 ALUctr Clk busW RegWr 32 32 busA 32 busB 5 5 5 Rw Ra Rb 32 32-bit Registers Rs Rt Rt Rd RegDst Extender Mux 32 16 imm16 ALUSrc ExtOp Mux MemtoReg Clk Data In WrEn 32 Adr Data Memory MemWr ALU Equal Instruction31:0 0 1 0 1 0 1 21:25 16:20 11:15 0:15 Imm16 Rd Rt Rs = Adder Adder PC Clk 00 Mux 4 nPC_sel PC Ext Adr Inst Memory 精品文档 CPU Design – Components of the Datapath Memory (MEM) instructions data Registers (R: 32 x 32) read RS read RT Write RT or RD PC Extender (sign extend) ALU (Add and Sub register or extended immediate) Add 4 or extended immediate to PC CPU Design – Instruction Implementation Instructions supported (for our sample processor): lw, sw beq R-format (add, sub, and, or, slt) corresponding I-format (addi …) You should be able to, given instructions, write control signals given control signals, write corresponding instructions in MIPS assembly What Does An ADD Look Like? imm16 32 ALUctr Clk busW RegWr 32 32 busA 32 busB 5 5 5 Rw Ra Rb 32 32-bit Registers Rs Rt Rt Rd RegDst Extender Mu