基于SPECMAN_E的DMC功能验证-微电子学与固体电子学专业论文.docxVIP

摘要 摘要 在SOC的设计中，数字逻辑电路的规模越来越大，现在平均门数已经在百万 门以上，在如此大规模电路的设计中功能验证已经成为IC设计的一个瓶颈，所以 设计团队不得不用500／0．．．70％的时间去进行功能验证，如此多的时间已经超过了进 行新代码开发的时间。而且随着规模的越来越大，其验证的难度也会成指数增长， 如果规模增加一倍，那么验证的难度就会是原难度的四倍。尽管耗去大量的时间 和人力，仍然会有一些边缘情况没有覆盖到，这样就导致了芯片流片的不成功。 于是业界提出了受限随机矢量生成验证方法学，即在满足条件约束的情况下随机 产生验证矢量。本文通过对DMC在SPECMAN．E的环境下的验证的介绍，对受 限随机矢量验证方法学进行了探索。 在本文中描述了使用E语言结合Vedlog语言验证的整个过程，首先根据DUT 的规范制定出验证计划和验证覆盖率的目标，画出验证环境结构图，接着使用E 语言和Vedlog语言对验证环境进行编程，产生激励和约束条件。最后对发现的错 误进行纠错，同时对功能覆盖率和代码覆盖率进行收集。最后对使用SPECMAN E 的优越性进行总结，对验证方法学发展进行了展望。 关键字：DMC SPECMAN．E 功能验证  Abstract As the average gate count for designs BOW approaches Or exceeds one million, functional verification has become the main bottlenec_k in the design process．Design teams spend 50％to 70％of their time verifying designs rather than creating new ones． As designs grow more complex,the verification problems increase exponentially when a design doubles in size，the verification effort call easily quadruple． Though，spend∞much resource and time，but there have SO many corners have not been cover,that result in the failure of the chip production．So a new functional verification methodology based 011 generation of constraint-random testbeneh is presented in industry．砀e methodology of functional verification can randomly generate the data with limited some constraints． We USe the verification platform of SPECMAN—E to verify the DMC(Dynamic memory Controller)，and research the new methodology base on the process of functional verification． 一 There have described the flow of verification with E language and Vcrilog language in this paper．First of all，We wrote the verification plan base on the specification of design, include function coverage，SOurCe code coverage require and drawn the environment． We write the environment code、衍m E language and Verilog HDL After completed the verification plan，and regenerated the stimulant and restrict．Last of all，We USe the SPECMAN—E and NC Verilog run the simulation and verification，debug the bug that found by SPEMCNA_