低抖动宽调谐电荷泵锁相环的研究与设计-电路与系统专业论文.docxVIP

上海交通大学工学硕士 上海交通大学工学硕士学位论文 ABSTRACT II II Research and Design of Low-Jitter Wide-Tuning Range Charge-Pump Phase-Lock Loops ABSTRACT With advancing VLSI technologies, a System-on-Chip (SoC) can integrate ever more functions, such as the acquisition, conversions, storage, processing, and I/O interfacing of signals, on a single chip. The premise of such implementations is reusable IP blocks, which means that various optimized modules can be reused as a unit into different new systems. One of the key components in this design paradigm is the PLL, which can produce variable yet accurate frequency signals from a reference input clock. The output signals can serve as the clock signals for certain digital systems or as the local oscillators for some communication systems. The motivation for this research is to implement a charge-pump PLL, which can provide a low-jitter, wide-tuning range and small-step programmable clock signal to support testing an analog-to-digital converter. The dissertation establishes a complete mathematical analysis based on a continuous-time approximation. The stability limit of the charge-pump PLL system is analyzed in detail. Then the behavior simulation is presented. Through this simulation, the circuit parameters are verified. The circuit design is highlighted in the dissertation. Various topologies of each module are introduced and analyzed thoroughly. Comparisons are then made in their speed, power consumption, area and stability. A new and improved charge-pump circuit is proposed and the self-biased VCO is optimized. Through these optimizations, we achieved improvements in chip area, power consumption, and phase jitter of this PLL. The prototype is implemented in HUAHONG 0.54μm CMOS process. The simulation results, demonstrating the improved performance of this charge-pump PLL, are also presented in this dissertation. KEY WORDS: SOC, PLL, charge-pump, low-jitter, wide-tuning range, self-biased, VCO 上海交通大学工学硕士 上海交通大学工学硕士学位论文 目录 PAGE PAG