首师大计组VHDL单周期CPU设计.docVIP

首师大计组VHDL单周期CPU设计 顶层文件： library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity CPU is port( --rw_address :out std_logic_vector(4 downto 0); --ra_address :out std_logic_vector(4 downto 0); --rb_address :out std_logic_vector(4 downto 0); --ra:out std_logic_vector(31 downto 0); --rb:out std_logic_vector(31 downto 0); --aluzero:out std_logic; --pc_address: out std_logic_vector(31 downto 0); clkzong: in std_logic; rst: in std_logic; --ALUout:out std_logic_vector(31 downto 0); DMdata:out std_logic_vector(31 downto 0); --RFwin:out std_logic_vector(31 downto 0); --ALUinB:out std_logic_vector(31 downto 0); --RegDst1,RegWrite1,ALUSrc1,MemtoReg1,MemWrite1,SEControl1:out std_logic; --NPCControl1:out std_logic_vector(1 downto 0); --ALUControl1:out std_logic_vector(2 downto 0); jdb18:out std_logic_vector(31 downto 0); jdb8:out std_logic_vector(31 downto 0); jdb16:out std_logic_vector(31 downto 0); jdb17:out std_logic_vector(31 downto 0); Zhiling:out std_logic_vector(31 downto 0)); end CPU; architecture Behavioral of CPU is component CU port( op:in std_logic_vector(5 downto 0); func:in std_logic_vector(5 downto 0); RegDst,RegWrite,ALUSrc,MemtoReg,MemWrite,SEControl:out std_logic; NPCControl:out std_logic_vector(1 downto 0); ALUControl:out std_logic_vector(2 downto 0)); end component; component NPC port( input:in std_logic_vector(31 downto 0); offset:in std_logic_vector(31 downto 0); pc:in std_logic_vector(31 downto 0); nNPCcontrol:in std_logic_vector(1 downto 0); ALUZero:in std_logic; npc1:out std_logic_vector(31 downto 0)); end component; component PC port(clk,clr:in std_logic; pc_in:in std_logic_vector(31 downto 0); pc_out:out std_logic_vector(31 downto 0)); end component; component dm PORT(clka:in std_logic; wea:in std_logic_vector(0 downto 0); addra:in std_logic_vector(7 downto 0); dina:in std_logic_vector(31 downto 0); douta:out std_logic_vector(31 downto 0)); end component; component im port(a:in std_logic_vector(7 downto 0); spo:out std_logic_