单周期七条指令cpu---计算机组成原理实验.docxVIP

各模块代码如下（编译通过且最终功能无误）module EXTENDER1(a,b);input [15:0]a;output [31:0]b;reg [31:0] b;always @ abeginb={16h0000,a};endendmodulemodule MUX2(alu_out,mem_out,mem_to_reg,busw);input [31:0] alu_out;input [31:0] mem_out;input mem_to_reg;output [31:0] busw;assign busw=mem_to_reg?alu_out:mem_out;endmodulemodule EXTENDER2(a,op,b);input [15:0]a;input op;output [31:0]b;reg [31:0] b;always@(a or op)if(op==0) b={16h0,a};else b={{16{a[15]}},a};endmodulemodule mips_tb(); reg clk, rst; MIPS MIPS( .clk(clk), .rst(rst) ); initial begin $readmemh( code.txt ,MIPS.INSTMemory.data); //$monitor(PC = 0x%8X, IR = 0x%8X, MIPS.PC.PC, MIPS.instr ); clk = 1 ; rst = 0 ; #5 ; rst = 1 ; #20 ; rst = 0 ; end always #(50) clk = ~clk;endmodulemodule INSTMemory(Adr, Dataout) ;input [31:0] Adr;output [31:0] Dataout;reg [31:0] Dataout;reg [31:0]data[31:0];always@ AdrbeginDataout=data[Adr];endendmodulemodule CONTROL(input clk,input [31:0] imem_out,output reg wr_en,output reg ext_op,output reg reg_wr,output reg [2:0] alu_ctr,output reg reg_dst,output reg alu_src,output reg npc_sel,output reg mem_to_reg,output reg jump);reg [5:0] imem_out06;always@(imem_out)beginif(imem_out[5:0]==6b100001imem_out[31:26]==6b000000) //addubeginext_op=0;jump=0;reg_wr=1;wr_en=0; reg_dst=1;npc_sel=0; mem_to_reg=0;alu_src=0;alu_ctr=3b000;endelse if(imem_out[5:0]==6b100011imem_out[31:26]==6b000000) //subbeginext_op=0;jump=0;reg_wr=1;wr_en=0; reg_dst=1;npc_sel=0;alu_src=0; mem_to_reg=0;alu_ctr=3b001;endelse if(imem_out[31:26]==6b001101) //oribeginext_op=0;jump=0;reg_wr=1;wr_en=0; reg_dst=0;npc_sel=0;alu_src=1; mem_to_reg=0;alu_ctr=3b011;endelse if(imem_out[31:26]==6b100011) //lwbeginext_op=0;jump=0; reg_wr=1;wr_en=0; reg_dst=0;npc_sel=0;alu_src=1; mem_to_reg=1;alu_ctr=3b000;endelse if(imem_out[31:26]==6b101011) //swbeginext_op=0;jump=0;reg_wr=0;wr_en=1; reg_dst=0;npc_sel=0;alu_src=1; mem_to_re