FIR Filter CMPE 222 – ProjectFIR滤波器CMPE 222–项目.pptVIP

FIR FilterCMPE 222 – Project Divya Misra Gnanapriya Mohanavelu FIR Filter Aim of the project Study the effect of latency Study the effect of type of adders on areatiming Understanding the synopsys tool Effect of taps on filters Terms used Coefficients Taps Memory No. of calculations Filtering Advantages Stop band attenuation Less ripple Narrower filter 3-tap filter Actual timing diagram 3-tap filter Architecture What we did Combinational circuit for addition Synthesis (had problems) All multiplications in the same stage Feeding constants externally Synthesis (had problems) Timing diagram with latency 5 Timing Diagram after reducing the latency to 3 Timing Diagram after increasing the latency to 6 Latency Synthesis list command Lists information about the commands,variables and licenses in the design analyzer or standard dc_shell e.g.: list link_library link_library = {typical.db} Shell script used for synthesis %dc_shell free –design alias veri “read –f verilog” veri fir.v veri fir_ctrl.v veri fir_dp.v link compile –map_effort medium –boundary_optimization Changing the type of adder dc_shellcurrent_design fir_dp dc_shell report_resources Implementation Report ========================================================================== | | | Current | Set | | Cell | Module | Implementation | Implementation | =========================================================================== | mult_30 | DW02_mult | csa | | | mult_36 | DW02_mult | csa | | | r124 | DW01_add | rpl | | ========================================================================== dc_shellset_implementation clf r124 dc_shell report_resources Changing the type of adder (contd.) Implementation Report ===