Catching Accurate Profiles i Hardware CECS在硬件 CECS捕捉准确的配置文件.pptVIP

Catching Accurate Profiles i Hardware CECS在硬件 CECS捕捉准确的配置文件.ppt

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Catching Accurate Profiles i Hardware CECS在硬件 CECS捕捉准确的配置文件

Catching Accurate Profiles in Hardware Satish Narayanasamy, Timothy Sherwood, Suleyman Sair, Brad Calder, George Varghese Outline Introduction Motivation Goal Related Work (Stratified Sampler) Interval-based Profiling for a Single Hash Profiler Experimental results Multiple-hash Profiler Experimental results Introduction Motivation SW – used to gather program behavior information Architectural support for generating profiles at run-time HW is used to assist SW, dependent on on system SW (for management or aggregation of events) HW-only profiler Introduction Motivation (cont.) HW optimizations that can take advantage of info gathered in run-time: Cache replacement prefetching identifying loads that cause majority of misses Value based optimization 50% of memory accesses are dominated by 10 distinct values capture this dynamically? = this information is used for storing compressed values in data cache Trace formation dynamically extracting and ordering frequently executed code = I-fetch more efficient Multiple path execution find branches that are hard to predict and execute down multiple paths Goal The goal is to build a profiling scheme that satisfies following properties: Area Efficient – capacity constraints (fixed amount of area) Accurate – identify important / frequent events and count them accurately Timely – up-to-date information about program behavior Performance Efficiency and SW Independence – independent of system SW support to manage profiles (accumulate and analyze events), identifying in HW Related Work SW profiling Binary instrumentation (ATOM by Calder et al.) HW counter assisted profiling DCPI system for Alpha Processors HW table based profiling Stratified sampling (Sastry et al.) Co-processor profiler Distill information passed from main processor (Ziles and Sohi) Profiling Events Profiling event: combination of several variables instruction PC, load address, register value or name, cache miss … Tuple represents event as combinatio

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