周期与周期的比较指令流线.ppt

Well, let’s look at a more complex example so I can show you how different instructions at different stages of execution can be processed by our pipelined datapath simultaneously. Let’s consider the following instruction sequence: Load, R-type, Store, and then Branch on equal to target address 1000. In the next four slides, I will show you the state of the datapath at the end of Cycle 4, Cycle 5, Cycle 6 and Cycle 7. First let’s take a look at the end of Cycle 4 where: (a) The Load instruction has just finished its Mem stage. (b) The R-type instruction has just finished its Exec stage. (c) The Store instruction has just finished its Register Fetch slash Instruction Decode stage. (d) And finally, the Branch instruction has just finish fetching the instruction. Remember now, the next four pictures we will be looking at are at the end of a clock cycle. That is right at the clock tick. +2 = 59 min. (Y:39) So the internal value of the register has just been updated BUT the output of the register, due to the Clock-to-Q delay, has NOT been changed to reflect the new internal value. The output of the register will still has the value from the cycle that has just ended. For example, look at Ifetch stage of the pipeline. The output of PC will still have the values of 12, the location of the Branch instruction even though PC has been updated to 16. Furthermore, the IF/ID register’s internal value have already been updated to the Branch instruction even though its output still contains the Store instruction so that we can read the registers (Ra and Rb) for the store instruction and store their values into the ID/Ex register. In order to get ready for calculating the store address, we also needs to pass the immediate field to the next stage. At the end of Cycle 4, the Exec stage of the pipeline have just completed the ALUOp for the R-type instruction so the ALU output is stored into the Exec/Mem register. Notice that for R-type instruction, the Rd field of the instruction is