操作系统Chapter07_OSMemory Management教程文件.pptVIP

7.2.4 Relocation 静态重定位 在程序执行之前由装配程序完成由虚拟地址到物理地址的转换过程 动态重定位 在程序的执行过程中，在CPU访问内存时所进行的由虚拟地址到物理地址的转换过程。 7.3.1 Paging Partition memory into small equal fixed-size chunks (called frames 帧) and divide each process into the same size chunks (called pages页) To run a program of size n pages, to find n free frames to load program. Page Tables for Example Operating system maintains a page table for each process Contains the frame location for each page in the process Paging How to translate logical address to physical address Logical address (page number页码, page offset页偏移) Page number (p) – used as an index into a page table which contains base address of each page in physical memory. Page offset (d) – combined with base address to define the physical memory address that is sent to the memory unit. Page table （页表）(The page table contains the base address of each page in physical memory) Physical address (frame number帧码, page offset页偏移) Paging 7.3.2 Paging: Page size Logical address 1 ? (5x4)+1 physical address Logical address 5 ? (6x4)+1 physical address 7.3.2 Paging: Page size How to partition logical addresses? The page size is selected as a power of 2. Possible page sizes: 总开销=s*e/p + p/2 求导得到 p = s=1MB , e = 8Byte ?p=4KB 512B ? 16MB ? Generally page sizes have grown over time as processes, data, and main memory have become larger. 7.3.3 Paging: Implementation of Page Table How to implement the page table Small, fast registers How to implement the page table Page table is kept in main memory. table base register (PTBR) points to the page table. In this scheme every data/instruction access requires two memory accesses. One for the page table and one for the data/instruction. 7.3.3 Paging: Implementation of Page Table 7.3.3 Paging: Implementation of Page Table The two memory access problem can be solved by the use of a special fast-lookup hardware cache called associative memory or translation look-aside buffers (TLBs) Associative memory – parallel search 7.