基于fpgaviterbi译码器实现word格式论文.docxVIP

ABSTRACTKeywords:convolution code, Viterbi decoder ,FPGA design目录第一章引言........................................................11.1研究背景及开发意义...........................................11.2本文工作...................................................21.3本文安排...................................................3第二章纠错码基本原理和卷积码原理..................................42.1数字通信系统的组成.........................................42.2差错控制系统分类...........................................52.2.1 重传反馈方式（ARQ）62.2.2 前向纠错方式（FEC）62.2.3 纠错方式（HEC）72.3纠错码的分类...............................................82.4线性分组码的基本概念.......................................92.4.1 线性分组码的生成矩阵.................................102.4.2 线性分组码的编码.....................................112.5卷积码基本原理............................................122.5.1 卷积码的生成矩阵.....................................142.5.2 卷积码编码...........................................162.6Viterbi译码算法192.6.1 卷积码的译码.........................................192.6 本章小结...................................................29第三章设计环境和设计方法.........................................303.1设计环境..................................................303.2设计方法..................................................313.3FPGA设计的基本原则333.4模块划分的技巧............................................363.5组合逻辑的注意事项........................................373.6Viterbi译码器的设计流程383.7小结......................................................384.2.3 分支量度模块的设计...................................444.2.4 加比选模块...........................................464.2.5 最小路径量度状态选择模块.............................484.2.6 溢出控制模块.........................................514.2.7 幸存信息管理.........................................544.2.8 其余模块的设计.......................................564.2.9 顶层设计.............................................564.2.10 下载验证............................................574.3 本章小结...................................................58第五章总结.....................................................59致谢......................................