Verilog作业.pdfVIP

Verilog 作业 1、8 位加法器 源代码adder.v module adder8(ina,inb,cin,cout,sum); input [7:0]ina ,inb; input cin; output [7:0] sum; output cout; assign {cout,sum}=ina+inb+cin; endmodule 测试代码 adder_tp.v `timescale 1ns/1ns `include adder.v module adder_tp; reg [7:0] a,b; reg cin; wire [7:0] sum; wire cout; adder8 adder(a,b,cin,cout,sum); always #5 cin = ~cin; initial begin a=0; b=0; cin=0; repeat(100) #10 a={$random}%256; //a is a random number between 0 and 255 end initial begin #10 b={$random}%256; //b is a random number between 0 and 255 end initial begin $monitor($time,,,%d+%d+%b={%b+%d},a,b,cin,cout,sum); #1000 $finish; end endmodule 2 8 、 位计数器 源代码count.v module count8(reset,clk,out); input reset; input clk; output [7:0] out; reg [7:0] out; always @(posedge clk) begin if(reset)out=0; else out =out+1; end endmodule 测试代码count_tp.v `timescale 1ns/1ns `include count.v module count_tp; reg clk,reset; wire [7:0] out; parameter DELY=100; count8 counter(reset,clk,out); always #(DELY/2) clk = ~clk; initial begin reset = 0; clk = 0; #DELYreset = 1; #DELYreset = 0; #(DELY*200) $finish; end initial $monitor($time,,,clk = %d reset = %d out = %d,clk,reset,out); endmodule 3 4 、 位移位寄存器 源代码 shifter.v //4 Bit shift Register module shifter( din, clk, rst, out ); input din; input rst; input clk; output[3:0] out; reg[3:0] out; always@(posedge clk) begin if(rst) out = 4b0; else begin out = out 1;