层次化设计——VHDL.docVIP

实验名称： 层次化设计——VHDL 班级： 09电气2Z 学号： 姓名： 钱雷 一、用层次化VHDL设计16选1选择器(用4个4选1选择器、1个2—4译码器和1个四输入或门扩展而成) 1.实体框图 2.程序设计 ①正确的程序 四选1选择器 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY MUX4B IS PORT(A,B,C,D,EN:IN STD_LOGIC; S1,S0:IN STD_LOGIC; Y:OUT STD_LOGIC); END ENTITY MUX4B; ARCHITECTURE TWO OF MUX4B IS SIGNAL S:STD_LOGIC_VECTOR(1 DOWNTO 0); BEGIN S=S1S0; Y=A WHEN S =00 AND EN =0 ELSE B WHEN S =01 AND EN =0 ELSE C WHEN S =10 AND EN =0 ELSE D WHEN S =11 AND EN =0 ELSE 0; END TWO; 2—4译码器 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY DECODER24 IS PORT(B,A:IN STD_LOGIC; Y3,Y2,Y1,Y0:OUT STD_LOGIC); END ENTITY DECODER24; ARCHITECTURE ONE OF DECODER24 IS SIGNAL INDATA:STD_LOGIC_VECTOR(1 DOWNTO 0); BEGIN INDATA=BA; PROCESS(INDATA) BEGIN CASE INDATA IS WHEN 00=Y3=1;Y2=1;Y1=1;Y0=0; WHEN 01=Y3=1;Y2=1;Y1=0;Y0=1; WHEN 10=Y3=1;Y2=0;Y1=1;Y0=1; WHEN 11=Y3=0;Y2=1;Y1=1;Y0=1; WHEN OTHERS =NULL; END CASE; END PROCESS; END ARCHITECTURE ONE ; 四输入或门 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY OR4A IS PORT(A,B,C,D:IN STD_LOGIC; Y:OUT STD_LOGIC); END ENTITY OR4A; ARCHITECTURE THREE OF OR4A IS BEGIN Y=A OR B OR C OR D; END ARCHITECTURE THREE; 顶层文件 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY MUX161A IS PORT(A3,A2,A1,A0,B3,B2,B1,B0,C3,C2,C1,C0,D3,D2,D1,D0,AIN,BIN,CIN,DIN:IN STD_LOGIC; YIN:OUT STD_LOGIC); END ENTITY MUX161A; ARCHITECTURE bb OF MUX161A IS COMPONENT DECODER24 PORT(A,B:IN STD_LOGIC; Y3,Y2,Y1,Y0:OUT STD_LOGIC); END COMPONENT; COMPONENT MUX4B PORT(A,B,C,D,EN,S1,S0:IN STD_LOGIC; Y:OUT STD_LOGIC); END COMPONENT; COMPONENT OR4A PORT(A,B,C,D:IN STD_LOGIC; Y:OUT STD_LOGIC); END COMPONENT; SIGNAL E,F,G,H,I,J,K,L:STD_LOGIC; BEGIN U1:DECODER24 PORT MAP(A=DIN,B=CIN,Y3=E,Y2=F,Y1=G,Y0=H); U2: MUX4B PORT MAP(S1=BIN,S0=AIN,A=A0,B=A1,C=A2,D=A3,EN=E,Y=I); U3:MUX4B PORT MAP(S1=BIN,S0=AIN,A=B0,B=B1,C=B2,D=B3,EN=F,Y=J); U4:MUX4B PORT MAP(