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ALU的VHDL设计
-- TOP
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_SIGNED.ALL;
ENTITY ALU IS
PORT(
AIN1,AIN2,AIN3,AIN4,BIN1,BIN2,BIN3,BIN4,CZ,DIN1,DIN2 : IN STD_LOGIC;
SUMM1,SUMM2,SUMM3,SUMM4,CO : OUT STD_LOGIC
);
END ENTITY ALU;
ARCHITECTURE BEHAV7 OF ALU IS
COMPONENT summary1
PORT(
A1,A2,A3,A4,B1,B2,B3,B4,C1,K1 : IN STD_LOGIC;
SUM1,SUM2,SUM3,SUM4,COUT1 : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT summary2
PORT(
A1,A2,A3,A4,C2,K2 : IN STD_LOGIC;
SUM1,SUM2,SUM3,SUM4,COUT2: OUT STD_LOGIC
);
END COMPONENT;
COMPONENT logic1
PORT(
A1,A2,A3,A4,B1,B2,B3,B4,C3,K3 : IN STD_LOGIC;
SUM1,SUM2,SUM3,SUM4 : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT logic2
PORT(
A1,A2,A3,A4,B1,B2,B3,B4,C4,K4 : IN STD_LOGIC;
SUM1,SUM2,SUM3,SUM4 : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT LogicCtrl
PORT(
D1,D2 : IN STD_LOGIC;
K11,K22,K33,K44 : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT or4a
PORT(
p1,q1,r1,s1 : IN STD_LOGIC;
t1 : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT or4b
PORT(
p2,q2,r2,s2 : IN STD_LOGIC;
t2 : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT or4c
PORT(
p3,q3,r3,s3 : IN STD_LOGIC;
t3 : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT or4d
PORT(
p4,q4,r4,s4 : IN STD_LOGIC;
t4 : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT or2a
PORT(
j,k : IN STD_LOGIC;
l : OUT STD_LOGIC
);
END COMPONENT;
SIGNAL W1,W2,W3,W4,W5,W6,W7,W8,W9,W10,W11,W12,W13,W14,
W15,W16,W17,W18,W19,W20,W21,W22 : STD_LOGIC;
BEGIN
U1 : LogicCtrl PORT MAP (D1 = DIN1, D2 = DIN2, K11 = W1,
K22 = W2, K33 = W3, K44 = W4);
U2 : summary1 PORT MAP ( A1 = AIN1, A2 = AIN2, A3 = AIN3,
A4 = AIN4, B1 = BIN1, B2 = BIN2,
B3 = BIN3, B4 = BIN4, C1 = CZ,
K1 = W1, SUM1 = W5, SUM2 = W6,
SUM3 = W7, SUM4 = W8, COUT1 = W9);
U3 : summary2 PORT MAP (A1 = AIN1, A2 = AIN2, A3 = AIN3,
A4 = AIN4, C2 = CZ
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