基于VHDL语言的数字时钟设计资料.docVIP

基于VHDL语言的数字时钟设计 专 业班级姓 名 2011年月日Jia ruoran (Grade09,Class2,Major of automation Dept. of automation of northeneast University at Qinhuangdao) Tutor:Ren Liangchao [Abstract] With the CPLD-based EDA technology and expansion of application fields and in-depth, EDA technology in electronic information, communication, automatic control areas such as the importance of computer is increasingly prominent. As a learning communications engineering students, we must continually learn more about new product information, it is even more requires us to have a full understanding of the EDA. The program design is based on VHDL digital clock, using EDA as a development tool, VHDL language for hardware description language, max+plusII as a program running platform, developed by the program to run through the debugging, waveform simulation, preliminary design goals achieved. This program uses the hardware description language VHDL, can greatly reduce the hardware of the entry-level digital system design, people feel that is closer to C language. Through this curriculum design, not only the students a better understanding of EDA technology in practical application, but also so that students have a comprehensive application of EDA deeper applications, this course designed for students to study and work after China has a comprehensive guide. [Key words] EDA Technology VHDL language Digital Clock Alarm Decode display Time Debugging [CLC] TN702 目 录 I．摘要………………………………………………………2 II．Astract……………..………………………….…………3 1.数字时钟设计任务…………………………………...……6 一. 系统功能描述……………………………..….…………8 二．设计方案的框图……………………………….………..8 2.1分频器的模块……… ………………….……………10 2.2秒计数器的模块……… ……… ……………………….11 2.3分计时器器模块……………… …………… ………….13 2.4小时计数模块……………… ...…………… …………..15 2.5扫描显示模块………………………...………………..17 2.6LED显示译码器模块………………. …..……………..18 2.7顶层原理图模块…………………...…………………..19 三．实验结果描述………………… ……...………………..19 四．心得体会………………………………