Hardware design examples using VHDL：使用VHDL硬件设计实例.pptVIP

VHDL8 Practical example v3b Address decode rules Decode the upper address lines using a decoder. Connect lower address lines directly to memory devices. * VHDL8 Practical example v3b Exercise 8.6 Fill in the modes (in, out, inout or buffer) of the input/output signal. SRAM (memory) CPU address lines (A0-A16) data lines (D0-D7) /CS,/OE and /WE lines * tRC ADD /CS /OE DOUT VHDL8 Practical example v2a * Exercise 8.7 Referring to the figure, what would happen if /RD of the CPU (connected to /OE) goes up before the data valid region occurs? tRC ADD /CS /OE DOUT VHDL8 Practical example v2a * Exercise 8.8 : Referring to the Figure, if tAS=0ns, twc=100ns,tCW=80ns, give comments on the limits of tAW, tWP and tDW.. ADD /CS /WE DIN tWC tCW tAW tDW tWP VHDL8 Practical example v3b Part 2 The sound recorder using a memory with parallel address bus * VHDL8 Practical example v3b The sound recorder Overall diagram Xilinx based hardware ram Reset Rec Play Digital to analog converter amplifier Analog to digital converter Microphone amplifier microphone DA0-7 AD0-7 * VHDL8 Practical example v3b Memory (32K) interface entity record1_entity is port ( --user inputs clk40k_in: in STD_LOGIC; reset, rec, play : in std_logic; -- for ram only bar_we27: buffer STD_LOGIC; bar_ram_we27: out STD_LOGIC; -- pin 27 w bar_ram_ce20: out STD_LOGIC; -- pin20 /E bar_ram_oe22: out STD_LOGIC; --pin22 G ram_address_buf: buffer std_logic_vector(14 downto 0); --A0-14 ram_data_inout: inout std_logic_vector(7 downto 0); --DQ0-7 da_data_out: buffer std_logic_vector(7 downto 0); --DA0-7 ad_data_in: in std_logic_vector(7 downto 0) ); --AD0-7 end; * VHDL8 Practical example v3b Static memory (SRAM 32Kbytes) data pins Diagrams are obtained from data sheet of M28256 at / Datasheet of a 64K Static Ram /webdocs/0b7b/0900766b80b7b917.pdf * VHDL8 Practical example v3b M28256 Memory read timing diagrams * VHDL8 Practical example v3b M2