106分频计数器的实现和仿真.docVIP

106 分频计数器的实现和仿真 程序如下： Library IEEE; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; ENTITY divider_1m IS PORT(clk : IN std_logic; clk1s : OUT std_logic); END divider_1m; ARCHITECTURE rt1 OF divider_1m IS SIGNAL cnt:INTEGER RANGE 0 TO 9; --SIGNAL cnt:INTEGER RANGE 0 TO 999999; 用于实际下载 BEGIN PROCESS(clk) BEGIN If (clkevent and clk=1)then If (cnt=cnthigh)then cnt=0; clk1s=1; Else cnt=cnt+1; clk1s=0; End if ; End if ; END PROCESS; END rt1; 计数器的VHDL描述 library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; ENTITY counter IS PORT( clk : IN std_logic; load : IN std_logic; buffertime : IN std_logic_vector(23 downto 0); time : OUT std_logic_vector(23 downto 0)); END counter; ARCHITECTURE rt1 OF counter IS SIGNAL clk1s : std_logic; SIGNAL time_sig: std_logic_vector(23 downto 0); Component divider_1m PORT( clk : IN std_logic; clk1s : OUT std_logic); End component; BEGIN divider1M:divider_1m Port map (clk = clk,clk1s = clk1s); PROCESS(clk1s,clk) BEGIN If (clkevent and clk=1)then If (load=1)then Time_sig=buffertime; Else If (clk1s=1)then If (Time_sig(3 downto 0) =1001)then Time_sig(3 downto 0) =0000; If (Time_sig(7 downto 4) =0101)then Time_sig(7 downto 4) =0000; If (Time_sig(11 downto 8) =1001)then Time_sig(11 downto 8) =0000; If (Time_sig(15 downto 12) =0101)then Time_sig(15 downto 12) =0000; If (Time_sig(23 downto 16) =001001)then Time_sig(23 downto 16) =010000; Elsif (time_sig(23 downto 16)=011001)then Time_sig(23 downto 16) =100000; Elsif (time_sig(23 downto 16)=100011)then Time_sig(23 downto 16) =000000; Else Time_sig(23 downto 16)= time_sig(23 downto 16)+1; End If ; Else Time_sig(15 downto 12)=Time_sig(15 downto 12)+1; End If ; Else Time_sig(11 downto 8)= time_sig(11 downto 8)+1; End If ; Else Time_sig(7 downto 4)= time_sig(7 downto 4)+1; End If ; Else Time_sig(3 downto 0)= time_sig(3 downto 0)+1; End I