EDA技术及应的用_第5章_5.pptVIP

* * 方法2：修改计数器（采用格雷码） * library ieee; use ieee.std_logic_1164.all; entity modcount is port(clk,reset:in std_logic; q:out std_logic_vector(2 downto 0)); end; architecture beh of modcount is constant r0:std_logic_vector(2 downto 0):=101; constant r1:std_logic_vector(2 downto 0):=100; constant r2:std_logic_vector(2 downto 0):=000; constant r3:std_logic_vector(2 downto 0):=001; constant r4:std_logic_vector(2 downto 0):=011; constant r5:std_logic_vector(2 downto 0):=010; constant r6:std_logic_vector(2 downto 0):=110; constant r7:std_logic_vector(2 downto 0):=111; signal count:std_logic_vector(2 downto 0); begin * process(clk,reset) begin if reset=1 then count=r0; elsif clkevent and clk=1 then case count is when r0=count=r1; when r1=count=r2; when r2=count=r3; when r3=count=r4; when r4=count=r5; when r5=count=r6; when r6=count=r7; when others=count=r0; end case; end if; end process; q=count; end; * * * 方法2： library ieee; use ieee.std_logic_1164.all; entity mealy2_2 is port(reset,clock,din:in std_logic; dout:out std_logic_vector(2 downto 0)); end; architecture behav of mealy2_2 is type state_type is(s0,s1,s2,s3); signal presentstate :state_type; signal nextstate :state_type; begin process(reset,clock) begin if reset=1 then presentstate=s0; elsif rising_edge(clock) then presentstate=nextstate; end if; end process; * process(presentstate,din) begin case presentstate is when s0=if din=1 then nextstate=s1;dout=001; else nextstate=s0;dout=000; end if; when s1=if din=1 then nextstate=s2;dout=011; else nextstate=s1;dout=010; end if; when s2=if din=1 then nextstate=s3;dout=101; else nextstate=s2;dout=100; end if; when s3=if din=1 then nextstate=s0;dout=111; else nextstate=s1;dout=110; end if; end case; end process; end; 在if语句内 * 例：用VHDL语言实现如图所示的mealy状态机----三进程的方法 library ieee; use ieee.std_logic_1164.all; entity mealy4 is port(reset,clock,din:in std_logic; dout:out std_logic_